# US 12,009,349 B2 · Vertical semiconductor package including horizontally stacked dies and methods of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,349 B2 - Document ID: US12009349B2 - Status: Granted - Kind: B2 - Application number: 17/476,703 - Filed: 2021-09-16 - Published: 2022-09-29 - Granted: 2024-06-11 - Earliest claimed: 2021-03-26 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Jen-Yuan Chang; Chia-Ping Lai - Web page: https://patentgrep.com/patent/US12009349B2 ## CPC - H10W 90/00: Package configurations - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/354: {comprising polymers} - H10W 72/801: {Interconnections on sidewalls of containers} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/792: {between multiple chips} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°. ## Claims ### Claim 1 A semiconductor package comprising: a first connection die comprising a first connection die substrate having a first connection die front side and an opposing first connection die back side that defines a plane of the first connection die, and a first connection die interconnect structure disposed on the first connection die front side; a second connection die comprising a second connection die substrate having a second connection die front side and an opposing second die backside that defines a plane of the second connection die, and a second connection die interconnect structure disposed on the second connection die front side; and first dies disposed in a first die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, each of the first dies comprising a first semiconductor substrate having a first die front side and an opposing first die backside that defines plane of the first die, and a first die interconnect structure disposed on the front side of the first semiconductor substrate and comprising a first die first connection line that is electrically connected to the first connection die interconnect structure, wherein an angle formed between the plane of the first connection die and the plane of a first die in the first die stack ranges from about 45° to about 90°, and wherein the plane of the first connection die is parallel to the plane of the second connection die. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first connection die interconnect structure electrically connects the first die first connection lines of at least two of the first dies directly to one another. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the planes of the first dies are perpendicular to the planes of the first connection die and second connection die. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein: the first dies comprise memory chips; and the first connection die is a passive component. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the first die stack comprises at least five of the first dies. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein: the first die first connection lines are exposed on the first side of the first die stack. ### Claim 7 (depends on 6) The semiconductor package of claim 6, wherein the first die interconnect structures each comprise a first die second connection line that is exposed on the second side of the first die stack and that is electrically connected to the second connection die interconnect structure. ### Claim 8 (depends on 1) The semiconductor package of claim 1, further comprising: second dies disposed in a second die stack disposed between the first connection die and the second connection die, each of the second dies comprising a second semiconductor substrate having a second die front side and an opposing second die backside that defines plane of the second die, and a second die interconnect structure comprising a second die first connection line that is electrically connected to the first connection die interconnect structure and a second die second connection line that is electrically connected to the second connection die. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein a plane of a second die of the second die stack is parallel to the plane of the first connection die. ### Claim 10 (depends on 8) The semiconductor package of claim 8, wherein a plane of a second die of the second die stack is perpendicular to the plane of the first connection die. ### Claim 11 A semiconductor package comprising: a first connection die comprising a first connection die substrate having a first connection die front side and an opposing first connection die backside that defines a plane of the first connection die, and a first connection die interconnect structure disposed on the first connection die front side; a second connection die comprising a second connection die substrate having a second connection die front side and an opposing second die backside that defines a plane of the second connection die, and a second connection die interconnect structure disposed on the second connection die front side; first dies disposed in a first die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, each of the first dies comprising a first semiconductor substrate having a first die front side and an opposing first die backside that defines a plane of the first die, and a first die interconnect structure disposed on the first die front side and comprising a first die first connection line that is exposed on the first side of the first die stack and electrically connected to the first connection die interconnect structure, and a first die second connection line that is exposed on the second side of the first die stack and electrically connected to the second connection die interconnect structure; and second dies disposed on the first connection die in a second die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, each of the second dies comprising a second semiconductor substrate having a second die front side and an opposing second die backside that defines a plane of the stacked second die, and second die interconnect structure comprising a second die first connection line that is electrically connected to the first connection die interconnect structure and a second die second connection line that is electrically connected to the second connection die interconnect structure, wherein the plane of a first die in the first die stack is perpendicular to the plane of the first connection die and the plane of the second connection die. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the first dies are stacked in a direction parallel to the plane of the first connection die. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein the plane of a second die is parallel to the plane of the first connection die. ### Claim 14 (depends on 11) The semiconductor package of claim 11, wherein the plane of each second die is perpendicular to the plane of the first connection die. ### Claim 15 (depends on 11) The semiconductor package of claim 11, wherein: the first connection die interconnect structure electrically connects the first die first connection lines of at least two of the first dies directly; and the first connection die interconnect structure electrically connects the second die first connection lines of at least two of the second dies directly. ### Claim 16 (depends on 11) The semiconductor package of claim 11, wherein: the first dies and the second dies comprise memory chips; and the first connection die is a passive component. ### Claim 17 (depends on 11) The semiconductor package of claim 11, wherein the second die first connection lines are exposed on the first side of the second die stack. ### Claim 18 (depends on 17) The semiconductor package of claim 17, a second die second connection lines are exposed on the second side of the second die stack. ### Claim 19 A semiconductor package comprising: a first connection die comprising a first connection die substrate having a first connection die front side and an opposing first connection die backside that defines a plane of the first connection die, and a first connection die interconnect structure disposed on the first connection die front side; a second connection die comprising a second connection die substrate having a second connection die front side and an opposing second die backside that defines a plane of the second connection die, and a second connection die interconnect structure disposed on the second connection die front side; and a first die stack having a first side that is bonded to the first connection die and an opposing second side that is bonded to the second connection die, the first die stack comprising first dies that are stacked on one another, each of the first dies comprising a first semiconductor substrate having a first die front side and an opposing first die backside that defines plane of the first die, and a first die interconnect structure disposed on the first die front side, the first die interconnect structure comprising a first die first connection line that is electrically connected to the first connection die interconnect structure and a first die second connection line that is electrically connected to the second connection die interconnect structure, wherein the plane of the first connection die is parallel to the plane of the second connection die, and wherein the first dies are stacked in a direction parallel to the planes of the first connection die and the second connection die. ### Claim 20 (depends on 19) The semiconductor package of claim 19, further comprising a second die stack having a second die first side that is bonded to the first connection die and an opposing second die second side that is bonded to the second connection die, the second die stack comprising second dies that are stacked on one another, each of the second dies comprising a second semiconductor substrate and a second die interconnect structure comprising a second die first connection line that is electrically connected to the first connection die interconnect structure and a second die second connection line that is electrically connected to the second connection die interconnect structure, wherein the second dies are stacked in a direction parallel to the planes of the first connection die and the second connection die.