# US 12,009,346 B2 · Semiconductor device and method of fabricating the same

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- Number: US 12,009,346 B2
- Document ID: US12009346B2
- Status: Granted
- Kind: B2
- Application number: 18/328,389
- Filed: 2023-06-02
- Published: 2023-09-28
- Granted: 2024-06-11
- Earliest claimed: 2018-08-24
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sung Min Kim; Dae Won Ha
- Web page: https://patentgrep.com/patent/US12009346B2

## CPC

- H10W 90/00: Package configurations
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/834: {comprising FinFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/218: {in silicon-on-insulator [SOI] wafers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
forming, in a first active region of a lower semiconductor substrate, a plurality of lower transistors, which comprise a plurality of lower gate structures and a plurality of lower source/drain regions;
forming, on the lower semiconductor substrate, a lower interlayer insulating film, covering the plurality of lower gate structures and the plurality of lower source/drain regions;
forming, in an upper semiconductor substrate, a plurality of upper transistors, which comprise a plurality of upper gate structures and a plurality of upper source/drain regions;
bonding the upper semiconductor substrate onto the lower interlayer insulating film;
after the bonding of the upper semiconductor substrate onto the lower interlayer insulating film, performing a first etching process to remove some of the plurality of upper gate structures and some of the plurality of upper source/drain regions;
after the bonding of the upper semiconductor substrate onto the lower interlayer insulating film, performing a second etching process to partially remove the upper semiconductor substrate; and
after the first etching process and the second etching process, forming a connection contact, connecting at least one of the plurality of lower transistors to at least one of the plurality of upper transistors.

### Claim 2 (depends on 1)

The method of fabricating a semiconductor device of claim 1, further comprising:
forming a lower source/drain contact and a lower landing pad connected to the lower source/drain region in the lower interlayer insulating film.

### Claim 3 (depends on 2)

The method of fabricating a semiconductor device of claim 2, wherein the plurality of lower transistors, the lower source/drain contact, and the lower landing pad are formed in a lower element region on the lower semiconductor substrate.

### Claim 4 (depends on 1)

The method of fabricating a semiconductor device of claim 1, wherein the forming of the plurality of upper transistors further comprising:
forming a plurality of pre-upper fin patterns extending in a first direction and the plurality of upper gate structures extending in a second direction intersecting the first direction to be regularly arranged on the upper semiconductor substrate.

### Claim 5 (depends on 4)

The method of fabricating a semiconductor device of claim 4, wherein the plurality of upper transistors is formed in an upper element region on the upper semiconductor substrate.

### Claim 6 (depends on 5)

The method of fabricating a semiconductor device of claim 5, further comprising:
removing a first portion of the upper semiconductor substrate to leave a second portion of the upper semiconductor substrate under the upper element region.

### Claim 7 (depends on 4)

The method of fabricating a semiconductor device of claim 4, further comprising:
forming misalignment of the pre-upper gate structures and the lower gate structures after the bonding of the upper semiconductor substrate and the lower semiconductor substrate, and
wherein the magnitude of the misalignment is less than half the distance between corresponding sidewalls of adjacent lower gate structures.

### Claim 8 (depends on 1)

The method of fabricating a semiconductor device of claim 1, wherein after the first etching process and the second etching process, a first upper semiconductor substrate, a plurality of first upper gate structures, a plurality of first upper source/drain regions, and a plurality of first upper fin patterns are formed in a region corresponding to the first active region.

### Claim 9 (depends on 8)

The method of fabricating a semiconductor device of claim 8, further comprising:
forming short sidewalls of upper gate electrodes and cut surfaces of first cut upper source/drain regions through the first etching process, and
forming sidewalls of the first upper semiconductor substrate through the second etching process.

### Claim 10 (depends on 9)

The method of fabricating a semiconductor device of claim 9, further comprising:
forming an upper interlayer insulating film on the lower interlayer insulating film covering the sidewalls of the first upper semiconductor substrate.

### Claim 11 (depends on 1)

The method of fabricating a semiconductor device of claim 1, wherein a mask pattern used in the first etching process is the same as a mask pattern used in the second etching process.

### Claim 12 (depends on 1)

The method of fabricating a semiconductor device of claim 1, wherein a mask pattern used in the first etching process is different from a mask pattern used in the second etching process.

### Claim 13

A method of fabricating a semiconductor device, the method comprising:
forming a lower semiconductor substrate;
forming a lower gate structure on the lower semiconductor substrate, the lower gate structure comprising a lower gate electrode;
forming a lower interlayer insulating film on the lower semiconductor substrate, the lower interlayer insulating film covering the lower gate structure;
forming an upper semiconductor substrate on the lower interlayer insulating film;
forming an upper gate structure on the lower interlayer insulating film; and
forming an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covering sidewalls of the upper semiconductor substrate,
wherein the upper gate structure comprises an upper gate electrode extending in a first direction, and upper gate spacers extending along sidewalls of the upper gate electrode,
wherein the upper gate electrode comprises long sidewalls extending in the first direction, and short sidewalls extending in a second direction, the second direction different from the first direction, and
wherein the upper gate spacers are on the long sidewalls of the upper gate electrode and are not on the short sidewalls of the upper gate electrode.

### Claim 14 (depends on 13)

The method of fabricating a semiconductor device of claim 13, further comprising:
forming a connection contact penetrating the upper semiconductor substrate, wherein the connection contact electrically connects a lower transistor to an upper transistor, the lower transistor comprising the lower gate electrode and the upper transistor comprising the upper gate electrode.

### Claim 15 (depends on 13)

The method of fabricating a semiconductor device of claim 13, further comprising:
forming a connection contact in the upper interlayer insulating film and in the lower interlayer insulating film, wherein
the connection contact electrically connects a lower transistor to an upper transistor, the lower transistor comprising the lower gate electrode, the upper transistor comprising the upper gate electrode,
the connection contact is on an upper surface of the lower semiconductor substrate which is not overlapped by the upper semiconductor substrate.

### Claim 16 (depends on 13)

The method of fabricating a semiconductor device of claim 13, wherein the lower gate structure, the upper semiconductor substrate and the upper gate structure are sequentially stacked on the lower semiconductor substrate.

### Claim 17 (depends on 13)

The method of fabricating a semiconductor device of claim 13, wherein the lower gate structure and the upper gate structure are between the lower semiconductor substrate and the upper semiconductor substrate.

### Claim 18 (depends on 13)

The method of fabricating a semiconductor device of claim 13, wherein, in the first direction, a portion of the upper gate structure protrudes further than the sidewalls of the upper semiconductor substrate.

### Claim 19 (depends on 13)

The method of fabricating a semiconductor device of claim 13, further comprising:
forming a lower gate contact which contacts the lower gate electrode;
forming a landing pad which contacts the lower gate contact; and
forming a connection contact which is connected to an upper transistor, the upper transistor comprising the upper gate electrode,
wherein the connection contact directly connects to the landing pad.

### Claim 20

A method of fabricating a semiconductor device, the method comprising:
forming a lower semiconductor substrate comprising a first region and a second region defined around the first region;
forming a plurality of lower transistors in the lower semiconductor substrate, the plurality of lower transistors comprising a plurality of lower gate structures and a plurality of lower source/drain regions, the plurality of lower gate structures extending in a first direction, and the plurality of lower source/drain regions being between the plurality of lower gate structures;
forming a lower interlayer insulating film on the lower semiconductor substrate, the lower interlayer insulating film covering the plurality of lower gate structures and the plurality of lower source/drain regions;
forming an upper semiconductor substrate on the lower interlayer insulating film of the first region of the lower semiconductor substrate;
forming an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covering sidewalls of the upper semiconductor substrate;
forming a plurality of upper transistors in the upper semiconductor substrate, the plurality of upper transistors being at positions overlapping the first region of the lower semiconductor substrate, the plurality of upper transistors comprising a plurality of upper gate structures and a plurality of upper source/drain regions, the plurality of upper gate structures extending in the first direction, and the plurality of upper source/drain regions being between the plurality of upper gate structures;
forming a first connection contact connecting at least one of the plurality of upper gate structures to at least one of the plurality of lower transistors; and
forming a second connection contact connecting at least one of the plurality of upper source/drain regions to at least one of the plurality of lower transistors,
wherein at least one of the first connection contact and the second connection contact penetrates the upper semiconductor substrate, and
wherein at least one of the lower transistor and the upper transistor includes a nanosheet.