# US 12,009,345 B2 · 3D package structure and methods of forming same

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- Number: US 12,009,345 B2
- Document ID: US12009345B2
- Status: Granted
- Kind: B2
- Application number: 18/149,509
- Filed: 2023-01-03
- Published: 2023-05-18
- Granted: 2024-06-11
- Earliest claimed: 2015-06-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Tse Chen; Chung-Shi Liu; Chih-Wei Lin; Hui-Min Huang; Hsuan-Ting Kuo; Ming-Da Cheng
- Web page: https://patentgrep.com/patent/US12009345B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/082: {the openings being tapered via holes}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 90/20: Configurations of stacked chips
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

## Claims

### Claim 1

A structure comprising:
a first die layer comprising:
a first die and a second die laterally encapsulated with an encapsulant, an upper surface of the encapsulant extending from a topmost point of the first die to a topmost point of the second die, an active side of the first die comprising a first conductive pad;
a first dielectric layer over the first die, the second die, and the encapsulant;
a first redistribution layer partially extending along a top surface of the first dielectric layer and extending through the first dielectric layer to physically contact the first conductive pad; and
a second die layer comprising:
a third die over the first dielectric layer and the first redistribution layer, the third die being encapsulated with a second dielectric layer, an active side of the third die comprising a second conductive pad; and
a through via extending from a top surface of the second dielectric layer to the first redistribution layer; and
a second redistribution layer extending from the top surface of the second dielectric layer to physically contact the second conductive pad of the third die, the second redistribution layer comprising a first seed layer being in physical contact with the second dielectric layer and the through via.

### Claim 2 (depends on 1)

The structure of claim 1, wherein a top surface of the through via and the top surface of the second dielectric layer are level.

### Claim 3 (depends on 2)

The structure of claim 2, wherein a lower surface of the first seed layer is in physical contact with the top surface of the through via and the top surface of the second dielectric layer.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the second dielectric layer is along lateral sides and a top surface of the third die.

### Claim 5 (depends on 1)

The structure of claim 1, wherein the encapsulant comprises a filler material embedded in a molding material.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the first dielectric layer is a different material than the encapsulant.

### Claim 7 (depends on 1)

The structure of claim 1, further comprising an external connector over the second dielectric layer and electrically coupled to the second redistribution layer.

### Claim 8 (depends on 7)

The structure of claim 7, wherein the external connector is electrically coupled to the through via.

### Claim 9

A structure comprising:
a first die, the first die having a first conductive pad and a passivation layer;
an encapsulant around lateral edges of the first die;
a first dielectric layer along top surfaces of the first die and the encapsulant;
a first redistribution layer disposed over the first dielectric layer, the first redistribution layer comprising a first via extending through the first dielectric layer and contacting the first conductive pad;
a second die over the first redistribution layer, the second die having a second conductive pad, a top surface of the first redistribution layer being interposed between a bottom surface of the second die and the first dielectric layer;
a second dielectric layer disposed over a top surface of the second die;
a second redistribution layer over the first redistribution layer and the second die, the second redistribution layer comprising a second via extending through the second dielectric layer and contacting the second conductive pad, the second redistribution layer further comprising a first level portion and a second level portion above an uppermost surface of the second dielectric layer, the second via and the second level portion comprising a continuous material; and
a through via extending from a first seed layer of the first level portion of the second redistribution layer to the top surface of the first redistribution layer.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the first die extends from a bottom surface to a top surface of the encapsulant.

### Claim 11 (depends on 9)

The structure of claim 9, wherein a thickness of the second dielectric layer is greater than a thickness of the second die.

### Claim 12 (depends on 9)

The structure of claim 9, wherein the first seed layer extends along an uppermost surface of the through via.

### Claim 13 (depends on 9)

The structure of claim 9, further comprising external connectors being electrically coupled to the second redistribution layer, the external connectors comprising a first connector and a second connector.

### Claim 14 (depends on 13)

The structure of claim 13, wherein the first connector is electrically coupled to the first die, and wherein the second connector is electrically coupled to the second die.

### Claim 15 (depends on 9)

The structure of claim 9, further comprising a third die adjacent to the first die, wherein the first redistribution layer comprises a third via extending through the first dielectric layer and contacting a third conductive pad of the third die.

### Claim 16

A structure comprising:
a first die laterally spaced from a second die;
a first dielectric layer laterally encapsulating the first die and the second die, a lower surface of the first dielectric layer being level with a lowermost point of the first die and a lowermost point of the second die, an upper surface of the first dielectric layer being level with an uppermost point of the first die and an uppermost point of the second die;
a second dielectric layer over and along the upper surface of the first dielectric layer;
a third die over the second dielectric layer;
a third dielectric layer encapsulating the third die, a thickness of the third dielectric layer being greater than a thickness of the third die;
a first redistribution layer extending from above a top surface of the second dielectric layer to a first conductive pad of the first die and to a second conductive pad of the second die;
a first through via extending from a top surface of the third dielectric layer to the first redistribution layer;
a second redistribution layer along the top surface of the third dielectric layer, the second redistribution layer comprising a second via extending to a third conductive pad of the third die; and
conductive connectors attached to the second redistribution layer, the conductive connectors comprising a first conductive connector, a second conductive connector, and a third conductive connector, the first conductive connector being electrically connected to the first die, the second conductive connector being electrically connected to the second die, the third conductive connector being electrically connected to the third die.

### Claim 17 (depends on 16)

The structure of claim 16, wherein a height of the first through via is greater than the thickness of the third die.

### Claim 18 (depends on 16)

The structure of claim 16, wherein the first dielectric layer and the third dielectric layer comprise different materials.

### Claim 19 (depends on 16)

The structure of claim 16, wherein the second redistribution layer comprises a seed layer, wherein a first portion of the seed layer extends along the top surface and a sidewall of the third dielectric layer to the third conductive pad of the third die.

### Claim 20 (depends on 19)

The structure of claim 19, wherein a second portion of the seed layer extends along the top surface of the third dielectric layer and a top surface of the first through via.