# US 12,009,344 B2 · Semiconductor package including stacked semiconductor chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,344 B2 - Document ID: US12009344B2 - Status: Granted - Kind: B2 - Application number: 17/200,063 - Filed: 2021-03-12 - Published: 2022-06-16 - Granted: 2024-06-11 - Earliest claimed: 2020-12-16 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Jin Kyoung Park - Web page: https://patentgrep.com/patent/US12009344B2 ## CPC - H10W 90/00: Package configurations - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 46/401: {for identification or tracking} - H10W 46/403: {for non-wireless electrical read out} - H10W 72/01515: {Forming coatings} - H10W 72/073: {of die-attach connectors} - H10W 72/075: {of bond wires} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/967: {Multiple bond pads having different functions} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 80/743: {having disposition changed during the connecting} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package including: a base layer; a first chip stack and a second chip stack sequentially stacked over the base layer, each of the first and second chip stacks including a plurality of semiconductor chips which are offset stacked to expose chip pads at one side edge thereof, and the chip pads including stack identification pads for identifying the first chip stack and the second chip stack and chip identification pads for identifying the plurality of semiconductor chips in each of the first and second chip stacks; a first inter-chip wire and a second inter-chip wire connecting power-applied ones of the chip identification pads of the plurality of semiconductor chips of the first and second chip stacks; a first stack wire and second stack wire connecting the chip identification pad of a lowermost semiconductor chip of the first and second chip stacks to the base layer. ## Claims ### Claim 1 A semiconductor package comprising: a base layer; a chip stack stacked over the base layer, the chip stack includes first to fourth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include chip identification pads; inter-chip wires connecting the chip identification pads of one semiconductor chip of the chip stack with the chip identification pads of adjacent semiconductor chip of the chip stack; and stack wires connecting the chip identification pads of the first semiconductor chip to the base layer, wherein the chip identification pads include first and second chip identification pads, wherein each of the first and second chip identification pads of the first semiconductor chip are connected to the base layer via the stack wires, wherein the inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip, wherein the inter-chip wires are configured to supply power to the first semiconductor chip through the first chip identification pad of the first semiconductor chip, wherein the inter-chip wires are configured to supply power to the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and wherein the inter-chip wires are configured to supply power to the third semiconductor chip through the second chip identification pad of the third semiconductor chip. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein the second chip identification pad of the first semiconductor chip, the second chip identification pad of the second semiconductor chip, the first chip identification pad of the third semiconductor chip, and the first and second chip identification pads of the fourth semiconductor chip are not connected to the inter-chip wires. ### Claim 3 (depends on 1) The semiconductor package according to claim 1, wherein the second chip identification pad of the first semiconductor chip, the second chip identification pad of the second semiconductor chip, the first chip identification pad of the third semiconductor chip, and the first and second chip identification pads of the fourth semiconductor chip are in a floating state. ### Claim 4 (depends on 1) The semiconductor package according to claim 1, wherein, in each of the first to fourth semiconductor chips, the chip identification pads are adjacent to each other. ### Claim 5 (depends on 1) The semiconductor package according to claim 1, wherein each of the first to fourth semiconductor chips further includes a stack identification pad adjacent to one of the chip identification pads. ### Claim 6 A semiconductor package comprising: a base layer; a first chip stack and a second chip stack stacked over the base layer, each of the first and second chip stacks including first to eighth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include stack identification pads and chip identification pads; first inter-chip wires connecting the chip identification pads of one semiconductor chip of the first chip stack with the chip identification pads of adjacent semiconductor chip of the first chip stack; first stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer; second inter-chip wires connecting the chip identification pads of one semiconductor chip of the second chip stack with the chip identification pads of adjacent semiconductor chip of the second chip stack; and second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer, wherein the chip identification pads include first to third chip identification pads, wherein the first, second, and third chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer via the first stack wires, respectively, wherein, in the first chip stack, the first inter-chip wires connect to two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the selected two chip identification pads of the second semiconductor chip, the selected two chip identification pads of the third semiconductor chip, and the selected two chip identification pads of the fourth semiconductor chip are different from each other, and wherein the selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other, wherein the first, second, and third chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer via the second stack wires, respectively, wherein, in the second chip stack, the second inter-chip wires connect two selected from the first to third chip identification pads of each of the second to fourth semiconductor chips, and one selected from the first to third chip identification pads of each of the fifth to seventh semiconductor chips, wherein the selected two chip identification pads of the second semiconductor chip, the selected two chip identification pads of the third semiconductor chip, and the selected two chip identification pads of the fourth semiconductor chip are different from each other, and wherein the selected one chip identification pad of the fifth semiconductor chip, the selected one chip identification pad of the sixth semiconductor chip, and the selected one chip identification pad of the seventh semiconductor chip are different from each other. ### Claim 7 (depends on 6) The semiconductor package according to claim 6, further comprising: a third inter-chip wire connecting the stack identification pad of one semiconductor chip of the first chip stack with the stack identification pad of adjacent semiconductor chip of the first chip stack; and a third stack wire connecting the stack identification pad of the first semiconductor chip of the first chip stack to the base layer. ### Claim 8 (depends on 7) The semiconductor package according to claim 7, wherein the stack identification pads of the first to eighth semiconductor chips of the second chip stack are not connected to the third inter-chip wires. ### Claim 9 (depends on 6) The semiconductor package according to claim 6, wherein, in each of the first to eighth semiconductor chips of each of the first and second chip stacks, the chip identification pads are adjacent to each other. ### Claim 10 (depends on 6) The semiconductor package according to claim 6, wherein, in each of the first to eighth semiconductor chips of each of the first and second chip stacks, the stack identification pad is adjacent to one of the chip identification pads. ### Claim 11 A semiconductor package comprising: a base layer; a first chip stack and a second chip stack stacked over the base layer, each of the first and second chip stacks including first to fourth semiconductor chips which are offset stacked to expose chip pads, wherein the chip pads include stack identification pads and chip identification pads; first inter-chip wires connecting the chip identification pads of one semiconductor chip of the first chip stack with the chip identification pads of adjacent semiconductor chip of the first chip stack; first stack wires connecting the chip identification pad of the first semiconductor chip of the first chip stack to the base layer; second inter-chip wires connecting the chip identification pads of one semiconductor chip of the second chip stack with the chip identification pads of adjacent semiconductor chip of the second chip stack; second stack wires connecting the chip identification pad of the first semiconductor chip of the second chip stack to the base layer, wherein the chip identification pads include first and second chip identification pads, wherein each of the first and second chip identification pads of the first semiconductor chip of the first chip stack are connected to the base layer via the first stack wires, wherein, in the first chip stack, the first inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip, wherein each of the first and second chip identification pads of the first semiconductor chip of the second chip stack are connected to the base layer via the second stack wires, wherein, in the second chip stack, the second inter-chip wires connect the first chip identification pad of the first semiconductor chip, the first chip identification pad of the second semiconductor chip, and the second chip identification pad of the third semiconductor chip, wherein, in the first chip stack, the first inter-chip wires are configured to supply power to: the first semiconductor chip through the first chip identification pad of the first semiconductor chip, the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and the third semiconductor chip through the second chip identification pad of the third semiconductor chip. ### Claim 12 (depends on 11) The semiconductor package according to claim 11, further comprising: a third inter-chip wire connecting the stack identification pad of one semiconductor chip of the first chip stack with the stack identification pad of adjacent semiconductor chip of the first chip stack; and a third stack wire connecting the stack identification pad of the first semiconductor chip of the first chip stack to the base layer. ### Claim 13 (depends on 12) The semiconductor package according to claim 12, wherein the stack identification pad of each of the first to fourth semiconductor chips of the second chip stack are not connected to the third inter-chip swire. ### Claim 14 (depends on 12) The semiconductor package according to claim 12, wherein the stack identification pad of each of the first to fourth semiconductor chips of the second chip stack are in a floating state. ### Claim 15 (depends on 11) The semiconductor package according to claim 11, wherein, in each of the first to fourth semiconductor chips of each of the first and second chip stacks, the chip identification pads are adjacent to each other. ### Claim 16 (depends on 11) The semiconductor package according to claim 11, wherein, in each of the first to fourth semiconductor chips of each of the first and second chip stacks, the stack identification pad is adjacent to one of the chip identification pads. ### Claim 17 (depends on 11) The semiconductor package according to claim 11, wherein, in the second chip stack, the second inter-chip wires are configured to supply power to: the first semiconductor chip through the first chip identification pad of the first semiconductor chip, the second semiconductor chip through the first chip identification pad of the second semiconductor chip, and the third semiconductor chip through the second chip identification pad of the third semiconductor chip. ### Claim 18 (depends on 12) The semiconductor package according to claim 12, wherein the third inter-chip wires are configured to supply power to the first to fourth semiconductor chips of the first chip stack through the stack identification pads of each of the the first to fourth semiconductor chips of the first chip stack.