# US 12,009,343 B1 · Stackable package and method

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- Number: US 12,009,343 B1
- Document ID: US12009343B1
- Status: Granted
- Kind: B1
- Application number: 15/347,545
- Filed: 2016-11-09
- Granted: 2024-06-11
- Earliest claimed: 2010-11-01
- Assignees: Amkor Technology Singapore Holding Pte. Ltd.
- Applicants: Amkor Technology Singapore Holding Pte. Ltd.
- Inventors: Robert Francis Darveaux; Roger D. St. Amand; Vladimir Perelman
- Web page: https://patentgrep.com/patent/US12009343B1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 40/10: Arrangements for heating
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/01515: {Forming coatings}
- H10W 72/075: {of bond wires}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on upper interconnection balls of the stackable package to force upper portions of the upper interconnection balls into the mold. However, lower portions of the upper interconnection balls are exposed within a space between the compliant surface and a substrate of the stackable package. The space is filled with a dielectric material to form a package body. The package body is formed while at the same time exposing the upper portions of upper interconnection balls from the package body in a single encapsulation operation. By avoiding selective removal of the package body to expose the upper interconnection balls, the number of operations as well as cost to manufacture the stackable package is minimized.

## Claims

### Claim 1

An electronic package comprising:
a substrate;
a first terminal on a first surface of the substrate;
an electronic component on the first surface of the substrate and coupled to the first terminal;
a second terminal on the first surface of the substrate;
a cylindrical interconnection structure on the first surface of the substrate and coupled to the second terminal; and
a package body on the first surface of the substrate and surrounding at least a portion of the cylindrical interconnection structure,
wherein the package body comprises a molded encapsulating material that directly contacts a plurality of lateral surfaces of the electronic component, and
wherein the cylindrical interconnection structure is laterally surrounded by the molded encapsulating material and comprises a copper column comprising:
a lower column portion that extends below a lowermost bottom surface of the molded encapsulating material, wherein no portion of the molded encapsulating material is below a lowermost side of the lower column portion; and
an upper column portion that protrudes upward from a top surface of the molded encapsulating material.

### Claim 2 (depends on 1)

The electronic package of claim 1, wherein the copper column comprises an uppermost surface that is substantially flat and free of connection with an upper electronic component.

### Claim 3 (depends on 1)

The electronic package of claim 1, wherein the copper column comprises plated copper.

### Claim 4 (depends on 1)

The electronic package of claim 1, comprising solder covering a top surface of the cylindrical interconnection structure.

### Claim 5 (depends on 1)

The electronic package of claim 1, wherein the package body is free of metal.

### Claim 6 (depends on 1)

The electronic package of claim 1, wherein the cylindrical interconnection structure comprises only the copper column.

### Claim 7 (depends on 1)

The electronic package of claim 1, wherein a top surface of the cylindrical interconnection structure is substantially flat when not connected to another electronic package.

### Claim 8 (depends on 1)

The electronic package of claim 1, wherein at least part of the upper column portion comprises a straight side surface that is orthogonal to the first surface of the substrate.

### Claim 9

A method of manufacturing an electronic package, the method comprising:
providing a substrate comprising:
a first terminal on a first surface of the substrate; and
a second terminal on the first surface of the substrate;
providing an electronic component on the first surface of the substrate and coupled to the first terminal;
providing a cylindrical interconnection structure on the first surface of the substrate and coupled to the second terminal; and
providing a package body on the first surface of the substrate and surrounding at least a portion of the cylindrical interconnection structure,
wherein the package body comprises a molded encapsulating material that directly contacts a plurality of lateral surfaces of the electronic component, and
wherein the cylindrical interconnection structure is laterally surrounded by the molded encapsulating material and comprises a copper column comprising:
a lower column portion that extends below a lowermost bottom surface of the molded encapsulating material, wherein no portion of the molded encapsulating material is below a lowermost side of the lower column portion; and
an upper column portion that protrudes upward from a top surface of the molded encapsulating material.

### Claim 10 (depends on 9)

The method of claim 9, wherein the copper column comprises an uppermost surface that is substantially flat and free of connection with an upper electronic component.

### Claim 11 (depends on 9)

The method of claim 9, wherein the package body is free of metal.

### Claim 12 (depends on 9)

The method of claim 9, wherein the cylindrical interconnection structure comprises only the copper column.

### Claim 13 (depends on 9)

The method of claim 9, wherein a top surface of the cylindrical interconnection structure is substantially flat when not connected to another electronic package.

### Claim 14 (depends on 9)

The method of claim 9, wherein at least part of the upper column portion comprises a straight side surface that is orthogonal to the first surface of the substrate.

### Claim 15 (depends on 9)

The method of claim 9, wherein said providing the cylindrical interconnection structure comprises plating the copper column.

### Claim 16 (depends on 9)

The method of claim 9, comprising forming solder covering a top surface of the cylindrical interconnection structure.

### Claim 17 (depends on 9)

The method of claim 9, comprising providing a solder mask on the first surface of the substrate, wherein the lowermost bottom surface of the molded encapsulating material directly contacts the solder mask.

### Claim 18 (depends on 1)

The electronic package of claim 1, comprising a solder mask on the first surface of the substrate, wherein the lowermost bottom surface of the molded encapsulating material directly contacts the solder mask.