# US 12,009,340 B2 · Method for fabricating electronic package

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- Number: US 12,009,340 B2
- Document ID: US12009340B2
- Status: Granted
- Kind: B2
- Application number: 17/481,610
- Filed: 2021-09-22
- Published: 2022-01-06
- Granted: 2024-06-11
- Earliest claimed: 2019-06-05
- Assignees: Siliconware Precision Industries Co., Ltd.
- Applicants: Siliconware Precision Industries Co., Ltd.
- Inventors: Lung-Yuan Wang; Feng Kao; Mao-Hua Yeh
- Web page: https://patentgrep.com/patent/US12009340B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/00: Package configurations
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/263: {Shielding bumps}
- H10W 42/273: {the arrangements being between laterally adjacent chips, e.g. walls between chips}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 74/01: Manufacture or treatment
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/721: {of bump connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

## Claims

### Claim 1

A method for fabricating an electronic package, comprising:
providing a first carrying structure having a first surface and a second surface opposing the first surface, with at least one first electronic component disposed on the first surface and electrically connected to the first carrying structure, and a plurality of conductors disposed on the second surface and electrically connected to the first carrying structure;
stacking on the first surface of the first carrying structure via at least one conductive element in a vertical direction a second carrying structure provided with a functional electronic component, wherein a lateral side surface of the functional electronic component faces and partially overlaps a lateral side surface of the first electronic component in a horizontal direction perpendicular to the vertical direction, and a top side surface of the functional electronic component does not face and overlap a top side surface of the first electronic component in the vertical direction; and
forming a packaging layer between the first carrying structure and the second carrying structure, allowing the packaging layer to pack the first electronic component, the functional electronic component and the conductive element.

### Claim 2 (depends on 1)

The method of claim 1, wherein the functional electronic component is electrically connected to the second carrying structure and electrically connects the conductive element to the first carrying structure and the second carrying structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein the conductive element is disposed on the second carrying structure, and then the conductive element is bonded onto the first carrying structure.

### Claim 4 (depends on 2)

The method of claim 2, wherein the conductive element is disposed on the first surface of the first carrying structure, and then the second carrying structure is bonded onto the conductive element.

### Claim 5 (depends on 2)

The method of claim 2, further comprising disposing at least one second electronic component on the second surface of the first carrying structure, and electrically connecting the second electronic component to the first carrying structure.

### Claim 6 (depends on 2)

The method of claim 2, further comprising forming an encapsulating layer on the second surface of the first carrying structure, and encapsulating the plurality of conductors with the encapsulating layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein a portion of a surface of the conductors is exposed from the encapsulating layer.

### Claim 8 (depends on 6)

The method of claim 6, further comprising disposing at least one second electronic component on the second surface of the first carrying structure and electrically connecting the second electronic component to the first carrying structure, wherein the encapsulating layer further encapsulates the second electronic component.

### Claim 9 (depends on 8)

The method of claim 8, wherein a portion of a surface of the second electronic component is exposed from the encapsulating layer.

### Claim 10 (depends on 2)

The method of claim 2, further comprising disposing a shielding structure on the first carrying structure or the second carrying structure, and packaging the shielding structure with the packaging layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the conductive element is disposed on the first surface of the first carrying structure or the second carrying structure, and the packaging layer is formed on the first surface of the first carrying structure or the second carrying structure.

### Claim 12 (depends on 11)

The method of claim 11, wherein before stacking the first carrying structure and the second carrying structure, the conductive element is disposed on one of the first carrying structure and the second carrying structure, and the packaging layer is formed on the other of the first carrying structure and the second carrying structure.

### Claim 13 (depends on 11)

The method of claim 11, wherein before stacking the first carrying structure and the second carrying structure, the conductive element is disposed on one of the first carrying structure and the second carrying structure, and the packaging layer packages the conductive element.
