# US 12,009,335 B2 · Structure and method of forming a joint assembly

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- Number: US 12,009,335 B2
- Document ID: US12009335B2
- Status: Granted
- Kind: B2
- Application number: 17/833,034
- Filed: 2022-06-06
- Published: 2022-09-22
- Granted: 2024-06-11
- Earliest claimed: 2016-05-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ying-Ju Chen; An-Jhih Su; Hsien-Wei Chen; Der-Chyang Yeh; Chi-Hsi Wu; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US12009335B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/073: {of die-attach connectors}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/01335: {by plating, e.g. electroless plating or electroplating}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

## Claims

### Claim 1

A device comprising:
a first semiconductor device comprising a first contact pad having a first surface contacting a metal feature, the first contact pad having a second surface opposite the first surface, the second surface being planar, wherein a ratio of a first width of the first surface to a second width of the second surface is 2:5;
a solder layer bonded to the first contact pad; and
a second semiconductor device comprising a second contact pad, the second contact pad having a third surface bonded to the solder layer, the second contact pad having a fourth surface opposite the third surface, the third surface being planar, wherein a ratio of a third width of the third surface to a fourth width of the fourth surface is 5:2, wherein the solder layer has tapered sidewalls continuously diminishing from the second width at a fifth surface adjoining the first contact pad to the third width at a sixth surface adjoining the second contact pad.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first semiconductor device further comprises an integrated passive device.

### Claim 3 (depends on 2)

The device of claim 2, wherein the integrated passive device comprises an impedance matching circuit, a harmonic filter, a bandpass filter, a low pass filter, a high pass filter, a coupler, a balun, a power combiner, or a power divider.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first contact pad comprises first vertical sidewalls extending from the first surface, and wherein the first contact pad comprises second vertical sidewalls extending from the second surface.

### Claim 5 (depends on 4)

The device of claim 4, wherein the second contact pad comprises third vertical sidewalls extending from the third surface, and wherein the second contact pad comprises first tapered sidewalls extending from the fourth surface.

### Claim 6 (depends on 5)

The device of claim 5, further comprising an encapsulant in contact with the first tapered sidewalls of the second contact pad.

### Claim 7 (depends on 6)

The device of claim 6, wherein the second contact pad contacts a redistribution layer, wherein the encapsulant contacts side surfaces of the redistribution layer.

### Claim 8

A device structure, comprising:
a first semiconductor device comprising an integrated passive device (IPD) in a package substrate and a first contact pad on the IPD, wherein a first portion of the first contact pad extends through the package substrate and is electrically coupled to the IPD, wherein the first contact pad has a first surface comprising first lateral extents, and wherein the first surface of the first contact pad is substantially planar;
a second semiconductor device comprising a redistribution layer (RDL) in an encapsulant and a second contact pad on the RDL, wherein a second portion of the second contact pad extends through the encapsulant and is electrically coupled to the RDL, wherein the second contact pad has a second surface comprising second lateral extents, wherein the second surface of the second contact pad is substantially planar, and wherein a first distance spanning the second lateral extents is less than a second distance spanning the first lateral extents; and
a joint structure between the first contact pad and the second contact pad, the joint structure comprising a solder layer, wherein the solder layer has a tapered sidewall profile extending with a continuously diminishing width from the first surface of the first contact pad to the second surface of the second contact pad, wherein a third surface of the joint structure contacting the first surface of the first contact pad comprises third lateral extents, wherein a third distance spanning the third lateral extents is equal to the second distance, wherein a fourth surface of the joint structure contacting the second surface of the second contact pad comprises fourth lateral extents, and wherein a fourth distance spanning the fourth lateral extents is equal to the first distance.

### Claim 9 (depends on 8)

The device structure of claim 8, wherein:
the first distance is less than or equal to about 50 μm;
the second distance is less than or equal to about 49 μm;
a first width of the first portion of the first contact pad is less than or equal to about 20 μm; and
a second width of the second portion of the second contact pad is less than or equal to about 20 μm.

### Claim 10 (depends on 8)

The device structure of claim 8, wherein at least one of the first contact pad or the second contact pad comprises copper, and wherein the solder layer comprises tin.

### Claim 11 (depends on 8)

The device structure of claim 8, wherein the second semiconductor device comprises a Package-on-Package (PoP) device.

### Claim 12 (depends on 11)

The device structure of claim 11, wherein the IPD comprises a capacitor, a resistor, an inductor, or a diode.

### Claim 13 (depends on 12)

The device structure of claim 12, wherein the first semiconductor device comprises an impedance matching circuit, a harmonic filter, a bandpass filter, a low pass filter, a high pass filter, a coupler, a balun, a power combiner, or a power divider.

### Claim 14 (depends on 8)

The device structure of claim 8, wherein the solder layer comprises a substantially continuous distribution of material between the first surface and the second surface.

### Claim 15 (depends on 14)

The device structure of claim 14, wherein the solder layer comprises a portion having a substantially oblate hemispheroidal shape along a principle axis vertically extending from the second surface to the first surface in a cross-sectional elevation view.

### Claim 16

A device comprising:
a first semiconductor device comprising a first contact pad extending into a package substrate, the first contact pad comprising a first surface contacting a metal feature, the first contact pad comprising a second surface opposite the first surface, wherein the second surface is planar;
a solder layer bonded to the first contact pad, the solder layer extending from a first lateral extent equal to a lateral extent of the second surface to a second lateral extent opposite the first lateral extent, wherein sidewalls of the first contact pad are free from the solder layer, wherein the second lateral extent is equal to a lateral extent of the third surface, wherein the solder layer has tapered sidewalls tapering from the first lateral extent to the second lateral extent; and
a second semiconductor device comprising a second contact pad extending through an encapsulant layer, the second contact pad having a third surface bonded to the solder layer, the second contact pad having a fourth surface opposite the third surface, wherein the third surface is planar, and wherein a ratio of a first width of the third surface to a second width of the fourth surface is 5:2, and further wherein the second surface has a third width greater than the first width.

### Claim 17 (depends on 16)

The device of claim 16, wherein the second surface has a third width, and wherein the third width is greater than the first width.

### Claim 18 (depends on 16)

The device of claim 16, wherein the second lateral extent is equal to a lateral extent of the third surface, wherein the solder layer has tapered sidewalls tapering from the first lateral extent to the second lateral extent.

### Claim 19 (depends on 16)

The device of claim 16, wherein the first semiconductor device further comprises an integrated passive device.

### Claim 20 (depends on 19)

The device of claim 19, wherein the integrated passive device comprises an impedance matching circuit, a harmonic filter, a bandpass filter, a low pass filter, a high pass filter, a coupler, a balun, a power combiner, or a power divider.