# US 12,009,333 B2 · Semiconductor device

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- Number: US 12,009,333 B2
- Document ID: US12009333B2
- Status: Granted
- Kind: B2
- Application number: 17/645,815
- Filed: 2021-12-23
- Published: 2022-04-14
- Granted: 2024-06-11
- Earliest claimed: 2018-08-06
- Assignees: Shinko Electric Industries Co., Ltd.
- Applicants: Shinko Electric Industries Co., Ltd.
- Inventors: Satoshi Shiraki
- Web page: https://patentgrep.com/patent/US12009333B2

## CPC

- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 72/30: Die-attach connectors
- H10W 20/48: Insulating materials thereof
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 70/458: {of insulating layers on leadframes}
- H10W 72/013: {of die-attach connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 76/12: characterised by their shape
- H10W 90/811: {Multiple chips on leadframes}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 72/01323: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01351: {Changing the shapes of die-attach connectors}
- H10W 72/01365: {Thermally treating (reflowing H10W72/01357)}
- H10W 72/07331: {Connecting techniques}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/075: {of bond wires}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/387: {Flow barriers}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/925: {Bond pads having a filler embedded in a matrix}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.

## Claims

### Claim 1

A semiconductor device, comprising:
a chip mounting member; and
a semiconductor chip bonded to the chip mounting member through a metal sintered material,
wherein the metal sintered material includes a first portion exactly overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the first portion in the plan view, the first portion and the second portion being arranged next to each other without a gap therebetween,
wherein a porosity ratio of the first portion is lower than a porosity ratio of the second portion, and
wherein a thickness of the first portion is less than a thickness of any part of the second portion.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein one surface of the second portion in contact with the chip mounting member is parallel to another surface of the second portion opposite the one surface.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising an insulating substrate having an interconnect layer disposed thereon, the interconnect layer being the chip mounting member.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising a lead frame having a die pad, the die pad being the chip mounting member.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein an entirety of the first portion has a lower porosity ratio than an entirety of the second portion, a boundary between the first portion and the second portion extending along an entire outer perimeter of the semiconductor chip.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the metal sintered material is a compressed metal sintered material, and the first portion and the second portion are each a compressed metal sintered portion.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the metal sintered material contains silver or copper.

### Claim 8

A method of making a semiconductor device, comprising:
printing a paste of a metal sintered material at and around a chip mounting area of a chip mounting member;
applying pressure to a periphery of the paste; and
bonding a semiconductor chip to the chip mounting member through the metal sintered material by applying pressure to the paste situated within the chip mounting area through the semiconductor chip in a heated atmosphere to sinter the paste situated at and around the chip mounting area to form the metal sintered material,
wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view,
wherein a porosity ratio of the first portion is lower than a porosity ratio of the second portion, and
wherein a thickness of the first portion is less than a thickness of the second portion.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein the porosity ratio of the second portion is lower than a porosity ratio of the printed paste observed immediately after printing the paste.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein the porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and the porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.

### Claim 11 (depends on 8)

The method as claimed in claim 8, wherein the second portion is thinner than a maximum thickness of the printed paste observed immediately after printing the paste, and the first portion is thinner than the second portion.

### Claim 12 (depends on 8)

The method as claimed in claim 8, wherein one surface of the second portion in contact with the chip mounting member is parallel to another surface of the second portion opposite the one surface.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein an area pressed by the step of applying pressure to the periphery of the paste is a frame-shaped area of the past extending from inside an outer boundary of the chip mounting area to an outermost periphery of the paste.

### Claim 14 (depends on 8)

The method as claimed in claim 8, wherein the step of applying pressure to the periphery of the paste applies pressure while heating the periphery of the paste, and wherein a heating temperature during the step of applying pressure to the periphery of the paste is lower than a heating temperature during the step of bonding the semiconductor chip.

### Claim 15 (depends on 8)

The method as claimed in claim 8, wherein the second portion is in direct contact with a side surface of the semiconductor chip.

### Claim 16 (depends on 8)

The method as claimed in claim 8, wherein the metal sintered material contains silver or copper.

### Claim 17 (depends on 8)

The method as claimed in claim 8, wherein the semiconductor device further includes an insulating substrate having an interconnect layer disposed thereon, the interconnect layer being the chip mounting member.

### Claim 18 (depends on 8)

The method as claimed in claim 8, wherein the semiconductor device further includes a lead frame having a die pad, the die pad being the chip mounting member.