# US 12,009,332 B2 · Semiconductor device having high yield strength intermediate plate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,332 B2 - Document ID: US12009332B2 - Status: Granted - Kind: B2 - Application number: 16/088,455 - Filed: 2016-07-28 - Published: 2019-05-23 - Granted: 2024-06-11 - Earliest claimed: 2016-07-28 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Yosuke Nakata; Taishi Sasaki - Web page: https://patentgrep.com/patent/US12009332B2 ## CPC - H10W 72/071: {Connecting or disconnecting} - H10W 72/076: {of strap connectors} - H10W 72/00: Interconnections or connectors in packages - H10W 72/07302: {using an auxiliary member} - H10W 72/07336: {Soldering or alloying} - H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature} - H10W 72/07354: {changes in dispositions} - H10W 72/07636: {Soldering or alloying} - H10W 72/347: {Dispositions of multiple die-attach connectors} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/383: {Reinforcing structures, e.g. collars} - H10W 72/652: {comprising metals or metalloids, e.g. silver} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor chip (3) is bonded to an upper surface of an electrode substrate (1) via a first solder (2). A lead frame (5) is bonded to an upper surface of the semiconductor chip (3) via a second solder (4). An intermediate plate (6) is provided in the first solder (2) between the electrode substrate (1) and the semiconductor chip (3). A yield strength of the intermediate plate (6) is higher than yield strengths of the electrode substrate (1) and the first solder (2) within the whole operating temperature range of the semiconductor device. ## Claims ### Claim 1 A semiconductor device comprising: an electrode substrate; a semiconductor chip bonded to an upper surface of the electrode substrate via a first solder; a lead frame bonded to an upper surface of the semiconductor chip via a second solder; an intermediate plate provided in the first solder between the electrode substrate and the semiconductor chip; and a plurality of bumps provided between the electrode substrate and the semiconductor chip, the plurality of bumps being comprised of wire, wherein a yield strength of the intermediate plate is higher than yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device, an outermost periphery of the intermediate plate is positioned inward of an outer periphery of the semiconductor chip and the first solder in planar view, the intermediate plate is positioned inward of the plurality of bumps in planar view, and the uppermost height of the bumps is less than a total thickness of the first solder, such that the bump does not contact the semiconductor chip. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the operating temperature range is −55° C. to 200° C. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein a distance between an end part of the semiconductor chip and an end part of the intermediate plate is larger than a thickness of the first solder. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the second solder is positioned inward of the intermediate plate in planar view. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising a plating film covering a surface of the intermediate plate and having higher wettability to the first solder than that of the intermediate plate. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein a main material of the plating film is nickel. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein a plurality of through holes are provided in the intermediate plate, and the plating film is provided on sidewalls of the plurality of through holes. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein a plurality of through holes are provided in the intermediate plate. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein a dimension of the through hole is 500 μmΦ or less. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the intermediate plate is smaller than a height of the plurality of bumps. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the semiconductor chip is 100 μm or less. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein a main material of the electrode substrate is aluminum. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein a main material of the intermediate plate is copper. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein a main material of the intermediate plate is molybdenum. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein a compound semiconductor is used for the semiconductor chip. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein a main material of the compound semiconductor includes carbon. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is used for a power supply which drives a motor for vehicular power. ### Claim 18 A semiconductor device comprising: an electrode substrate; a semiconductor chip bonded to an upper surface of the electrode substrate via a first solder; a lead frame directly bonded to an upper surface of the semiconductor chip via a second solder; an intermediate plate provided in the first solder between the electrode substrate and the semiconductor chip; and a plurality of bumps provided between the electrode substrate and the semiconductor chip, the plurality of bumps being comprised of wire, wherein a yield strength of the intermediate plate is higher than yield strengths of the electrode substrate and the first solder within the whole operating temperature range of the semiconductor device, an outer periphery of the intermediate plate is positioned inward of an outer periphery of the semiconductor chip and the first solder in planar view, the intermediate plate is positioned inward of the plurality of bumps in planar view, and the uppermost height of the bumps is less than a total thickness of the first solder, such that the bump does not contact the semiconductor chip. ### Claim 19 (depends on 18) The semiconductor device according to claim 18, wherein a thickness of the intermediate plate is smaller than a height of the plurality of bumps.