# US 12,009,331 B2 · Integrated circuit packages having adhesion layers for through vias

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- Number: US 12,009,331 B2
- Document ID: US12009331B2
- Status: Granted
- Kind: B2
- Application number: 18/330,616
- Filed: 2023-06-07
- Published: 2023-10-05
- Granted: 2024-06-11
- Earliest claimed: 2021-03-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Chun Cho; Sih-Hao Liao; Yu-Hsiang Hu; Hung-Jui Kuo
- Web page: https://patentgrep.com/patent/US12009331B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/6525: {for securing the interconnections to the substrate, e.g. to prevent peeling}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

## Claims

### Claim 1

A device comprising:
a semiconductor die comprising a semiconductor material;
a through via adjacent the semiconductor die, the through via comprising a metal;
an encapsulant around the through via and the semiconductor die, the encapsulant comprising a polymer resin; and
an adhesion layer between the encapsulant and the through via, the adhesion layer comprising an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

### Claim 2 (depends on 1)

The device of claim 1, wherein the aromatic compound is an azole compound and the polymer resin is an epoxy resin.

### Claim 3 (depends on 1)

The device of claim 1 further comprising:
a dielectric layer comprising a dielectric material, the aromatic compound being chemically inert to the dielectric material of the dielectric layer; and
an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer, the through via disposed on the line portion of the under-bump metallurgy layer.

### Claim 4 (depends on 1)

The device of claim 1, wherein the semiconductor die is an integrated circuit die.

### Claim 5 (depends on 1)

The device of claim 1, wherein the semiconductor die is an interconnection die.

### Claim 6

A device comprising:
a first integrated circuit die comprising a die connector;
a first encapsulant around the first integrated circuit die;
a first dielectric layer on the first encapsulant and the first integrated circuit die;
a conductive feature comprising a metal layer having a lower via portion, a line portion, and an upper via portion, the lower via portion extending through the first dielectric layer to be connected to the die connector of the first integrated circuit die, the line portion extending along the first dielectric layer, the upper via portion disposed on the line portion, the upper via portion laterally offset from the lower via portion;
a first adhesion layer extending along sidewalls of the line portion and the upper via portion of the conductive feature, a material of the first adhesion layer bonded to a material of the conductive feature; and
a second encapsulant around the first adhesion layer, a material of the second encapsulant bonded to the material of the first adhesion layer.

### Claim 7 (depends on 6)

The device of claim 6 further comprising:
a second integrated circuit die, the first encapsulant disposed around the second integrated circuit die; and
an interconnection die, the second encapsulant disposed around the interconnection die, the interconnection die connecting the first integrated circuit die to the second integrated circuit die.

### Claim 8 (depends on 6)

The device of claim 6 further comprising:
a redistribution structure on the second encapsulant, the first adhesion layer, and the conductive feature, the redistribution structure comprising a redistribution line connected to the conductive feature; and
a package substrate connected to the redistribution line of the redistribution structure.

### Claim 9 (depends on 8)

The device of claim 8, wherein the redistribution structure further comprises:
a second adhesion layer on surfaces of the redistribution line, a material of the second adhesion layer bonded to a material of the redistribution line; and
a second dielectric layer around the second adhesion layer, a material of the second dielectric layer bonded to the material of the second adhesion layer.

### Claim 10 (depends on 6)

The device of claim 6, wherein top surfaces of the second encapsulant, the first adhesion layer, and the conductive feature are substantially coplanar.

### Claim 11 (depends on 6)

The device of claim 6, wherein top surfaces of the second encapsulant and the first adhesion layer are substantially coplanar, and a top surface of the conductive feature is recessed from the top surfaces of the second encapsulant and the first adhesion layer.

### Claim 12 (depends on 6)

The device of claim 6, wherein the material of the first adhesion layer comprises a nitrogen-containing aromatic compound and an amine.

### Claim 13 (depends on 12)

The device of claim 12, wherein the nitrogen-containing aromatic compound is an azole compound and the amine is an amino group.

### Claim 14

A device comprising:
a through via comprising a metal;
an adhesion layer on the through via, the adhesion layer comprising an adhesive compound, the adhesive compound of the adhesion layer covalently bonded to the metal of the through via;
an encapsulant around the adhesion layer, the encapsulant comprising an encapsulating material, the encapsulating material of the encapsulant covalently bonded to the adhesive compound of the adhesion layer; and
a redistribution structure on the encapsulant, the redistribution structure comprising a redistribution line connected to the through via.

### Claim 15 (depends on 14)

The device of claim 14, wherein a top surface of the through via is substantially coplanar with a top surface of the encapsulant.

### Claim 16 (depends on 14)

The device of claim 14, wherein a top surface of the through via is recessed from a top surface of the encapsulant.

### Claim 17 (depends on 14)

The device of claim 14, wherein the adhesion layer is one monolayer of the adhesive compound.

### Claim 18 (depends on 14)

The device of claim 14, wherein the adhesion layer is a plurality of monolayers of the adhesive compound.

### Claim 19 (depends on 14)

The device of claim 14, further comprising:
an integrated circuit die adjacent the through via, the encapsulant disposed around the integrated circuit die.

### Claim 20 (depends on 14)

The device of claim 14, further comprising:
an interconnection die adjacent the through via, the encapsulant disposed around the interconnection die.