# US 12,009,328 B2 · Semiconductor package and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,328 B2 - Document ID: US12009328B2 - Status: Granted - Kind: B2 - Application number: 17/715,479 - Filed: 2022-04-07 - Published: 2022-07-21 - Granted: 2024-06-11 - Earliest claimed: 2020-02-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyunsoo Chung; Taewon Yoo; Myungkee Chung - Web page: https://patentgrep.com/patent/US12009328B2 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/019: {of bond pads} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/01257: {by reflowing} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01955: {by using masks} - H10W 72/072: {of bump connectors} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/354: {comprising polymers} - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/931: {Shapes of bond pads} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface. ## Claims ### Claim 1 A semiconductor package, comprising: a semiconductor chip including a pad; a first insulation pattern on an upper surface of the semiconductor chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and electrically connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern, the second insulation pattern including at least one opening that exposes a ball land of the RDL and at least one patterned portion located in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and the patterned portion and filling the opening, the UBM including a first hole that exposes an edge portion of an upper surface of the ball land and at least one branch that crosses the first hole in a radial direction of the UBM; and a conductive ball on an upper surface of the UBM, the conductive ball including a first locking portion in the first hole, wherein the first hole has an area of about 10% to about 50% of an area of the upper surface of the UBM. ### Claim 2 (depends on 1) The semiconductor package as claimed in claim 1, wherein the first hole has an annular shape. ### Claim 3 (depends on 1) The semiconductor package as claimed in claim 1, wherein: the UBM further includes a second hole located in the first hole and exposing a central portion of the upper surface of the ball land, and the conductive ball further includes a second locking portion in the second hole. ### Claim 4 (depends on 1) The semiconductor package as claimed in claim 1, wherein: the UBM further includes a peripheral hole that exposes the upper surface of the second insulation pattern, and the conductive ball further includes a peripheral locking portion in the peripheral hole. ### Claim 5 (depends on 4) The semiconductor package as claimed in claim 4, wherein the peripheral hole surrounds the first hole. ### Claim 6 (depends on 1) The semiconductor package as claimed in claim 1, further comprising a seed layer interposed between the second insulation pattern and the UBM, and interposed between the RDL and the UBM. ### Claim 7 (depends on 6) The semiconductor package as claimed in claim 6, further comprising a barrier layer interposed between the seed layer and the second insulation pattern, and interposed between the seed layer and the RDL. ### Claim 8 A semiconductor package, comprising: a semiconductor chip including a pad; a first insulation pattern on an upper surface of the semiconductor chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and electrically connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern, the second insulation pattern including at least one opening that exposes a ball land of the RDL, and at least one patterned portion located in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and the patterned portion and filling the opening, the UBM including a hole and at least one branch that crosses the hole in a radial direction of the UBM; and a conductive ball on an upper surface of the UBM, the conductive ball including a locking portion in the hole. ### Claim 9 (depends on 8) The semiconductor package as claimed in claim 8, wherein the hole includes: a first hole that exposes an edge portion of an upper surface of the ball land; and a second hole that exposes a central portion of the upper surface of the ball land. ### Claim 10 (depends on 9) The semiconductor package as claimed in claim 9, wherein the locking portion includes: a first locking portion in the first hole; and a second locking portion in the second hole. ### Claim 11 (depends on 8) The semiconductor package as claimed in claim 8, wherein the hole has an area of about 10% to about 50% of an area of the upper surface of the UBM. ### Claim 12 (depends on 8) The semiconductor package as claimed in claim 8, wherein the hole has an annular shape. ### Claim 13 (depends on 12) The semiconductor package as claimed in claim 12, wherein the hole has an upper width and a lower width narrower than the upper width. ### Claim 14 (depends on 8) The semiconductor package as claimed in claim 8, wherein: the UBM further includes a peripheral hole that exposes the upper surface of the second insulation pattern, and the conductive ball further includes a peripheral locking portion in the peripheral hole. ### Claim 15 (depends on 14) The semiconductor package as claimed in claim 14, wherein the peripheral hole surrounds the hole. ### Claim 16 (depends on 8) The semiconductor package as claimed in claim 8, further comprising a seed layer interposed between the second insulation pattern and the UBM, and interposed between the RDL and the UBM. ### Claim 17 (depends on 16) The semiconductor package as claimed in claim 16, further comprising a barrier layer interposed between the seed layer and the second insulation pattern, and interposed between the seed layer and the RDL. ### Claim 18 A method of manufacturing a semiconductor package, the method comprising: forming a first insulation pattern on an upper surface of a semiconductor chip to expose a pad of the semiconductor chip; forming a redistribution layer (RDL) on an upper surface of the first insulation pattern, the RDL being electrically connected to the pad; forming a second insulation pattern on the upper surface of the first insulation pattern, the second insulation pattern including at least one opening that exposes a ball land of the RDL and including at least one patterned portion located in the opening; forming an under bump metal (UBM) on upper surfaces of the second insulation pattern and the patterned portion to fill the opening, the UBM including a hole that exposes the ball land and at least one branch that crosses the hole in a radial direction of the UBM; and forming a conductive ball on an upper surface of the UBM, the conductive ball including a locking portion inserted into the hole. ### Claim 19 (depends on 18) The method as claimed in claim 18, wherein forming the UBM having the hole includes: forming a first hole through the UBM to expose an edge portion of an upper surface of the ball land; and forming a second hole through the UBM to expose a central portion of the upper surface of the ball land. ### Claim 20 (depends on 18) The method as claimed in claim 18, further comprising forming a peripheral hole through the UBM to expose the upper surface of the second insulation pattern, wherein forming the conductive ball further includes filling the peripheral hole with the conductive ball.