# US 12,009,327 B2 · Semiconductor die > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,327 B2 - Document ID: US12009327B2 - Status: Granted - Kind: B2 - Application number: 17/461,952 - Filed: 2021-08-30 - Published: 2023-03-02 - Granted: 2024-06-11 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yen-Kun Lai; Chien-Hao Hsu; Wei-Hsiang Tu; Kuo-Chin Chang; Mirng-Ji Lii - Web page: https://patentgrep.com/patent/US12009327B2 ## CPC - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/42: Vias, e.g. via plugs - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/981: {Auxiliary members, e.g. spacers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via. ## Claims ### Claim 1 A semiconductor die, comprising: a semiconductor substrate, an interconnect structure disposed on and electrically connected to the semiconductor substrate, the interconnect structure comprising: stacked interconnect layers, each of the stacked interconnect layers comprising a dielectric layer and an interconnect wiring embedded in the dielectric layer, wherein the interconnect wiring of a first interconnect layer among the stacked interconnect layers further comprises: a first via electrically connected to the interconnect wiring; second vias connected to the interconnect wiring, wherein the first via and the second vias are located on a same level height, wherein the second vias are electrically insulated from the first via; and a conductive bump disposed on the interconnect structure, wherein the conductive bump comprises a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via. ### Claim 2 (depends on 1) The semiconductor die of claim 1, wherein the interconnect structure further comprises: a second interconnect layer among the stacked interconnect layers, the second interconnect layer being disposed under the first interconnect layer, and the second interconnect layer comprising: a second dielectric layer; a second interconnect wiring; and a third via electrically connected to the second interconnect wiring, wherein the third via overlaps the first via. ### Claim 3 (depends on 2) The semiconductor die of claim 2, wherein the interconnect wiring of the first interconnect layer comprises a first conductive portion and a first peripheral portion electrically insulated from the first peripheral portion, the first conductive portion connects to the first via, and the first peripheral portion connects to at least one of the second vias. ### Claim 4 (depends on 3) The semiconductor die of claim 3, wherein the interconnect wiring of the second interconnect layer comprises a second conductive portion and a second peripheral portion electrically insulated from the second conductive portion, the second conductive portion connects to the first via and the third via, and the second peripheral portion connects to at least one of the second vias. ### Claim 5 (depends on 1) The semiconductor die of claim 1, wherein the dielectric layer has a dielectric constant between 2.0 to 3.0. ### Claim 6 (depends on 1) The semiconductor die of claim 1, further comprising an insulating layer and a metallization pattern embedded in the insulating layer, wherein the metallization pattern is disposed between the interconnect structure and the conductive bump. ### Claim 7 (depends on 6) The semiconductor die of claim 6, further comprising a metallization via, the metallization via electrically connected the interconnect structure to metallization pattern. ### Claim 8 (depends on 7) The semiconductor die of claim 7, wherein the first via is disposed under the metallization via. ### Claim 9 (depends on 1) The semiconductor die of claim 1, further comprising a conductive pad disposed between the interconnect structure and the conductive bump, wherein the conductive pad is electrically connected to the interconnect structure and the conductive bump. ### Claim 10 (depends on 9) The semiconductor die of claim 9, further comprising a first passivation layer and a second passivation layer, the first passivation layer is disposed on the interconnect structure, the second passivation layer is disposed on the first passivation layer, and the conductive pad is covered by the second passivation layer. ### Claim 11 (depends on 1) The semiconductor die of claim 1, further comprising another insulating layer, wherein the protruding portion of the conductive bump is disposed over the another insulating layer, the base portion of the conductive bump is embedded in the another insulating layer, and the base portion electrically connects to the conductive pad. ### Claim 12 A semiconductor die, comprising: a semiconductor substrate, an interconnect structure disposed on and electrically connected to the semiconductor substrate, the interconnect structure comprising: a first interconnect layer comprising a first dielectric layer, a first interconnect wiring embedded in the first dielectric layer, a first via and second vias; and a second interconnect layer disposed on the first interconnect layer, the second interconnect layer comprising a second dielectric layer and a second interconnect wiring embedded in the second dielectric layer, wherein the first via is disposed between the first interconnect wiring and the second interconnect wiring, the first via electrically connects the first interconnect wiring to the second interconnect wiring, and the second vias are disposed between the first interconnect wiring and the second interconnect wiring; and an insulating layer and a metallization pattern disposed on the interconnect structure, wherein the metallization pattern is embedded in the insulating layer, wherein the first dielectric layer is a topmost layer of the interconnect structure, the insulating layer is disposed over the first dielectric layer, and a dielectric constant of the first dielectric layer is less than a dielectric constant of the insulating layer, wherein the first via and the second vias are embedded in the first dielectric layer, and the first via is spaced apart from the second vias, and the second vias are electrically insulated from the first via. ### Claim 13 (depends on 12) The semiconductor die of claim 12, further comprising: a conductive bump disposed on the interconnect structure, wherein the conductive bump comprises a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via; and a conductive pad disposed between the interconnect structure and the conductive bump, wherein the conductive pad is electrically connected to the interconnect structure and the base portion of the conductive bump. ### Claim 14 (depends on 13) The semiconductor die of claim 13, further comprising a first passivation layer and a second passivation layer, the first passivation layer is disposed on the interconnect structure, the second passivation layer is disposed on the first passivation layer, and the conductive pad is embedded in the second passivation layer. ### Claim 15 (depends on 13) The semiconductor die of claim 13, further comprising a metallization via electrically connected the interconnect structure to the metallization pattern, wherein the metallization pattern is between the interconnect structure and the conductive pad. ### Claim 16 (depends on 15) The semiconductor die of claim 15, wherein the first via, the second vias, and the metallization via are disposed under the base portion of the conductive bump. ### Claim 17 (depends on 13) The semiconductor die of claim 13, wherein the second vias are connected to the first interconnect wiring, and the second vias are connected to each other. ### Claim 18 A semiconductor die, comprising: a semiconductor substrate, an interconnect structure disposed on and electrically connected to the semiconductor substrate, the interconnect structure comprising: a first interconnect layer comprising a first dielectric layer, a first interconnect wiring embedded in the first dielectric layer, a conduction via and at least one stress release via; and a second interconnect layer disposed on the first interconnect layer, the second interconnect layer comprising a second dielectric layer and a second interconnect wiring embedded in the second dielectric layer, wherein the conduction via is disposed between the first interconnect wiring and the second interconnect wiring, and the at least one stress release via is disposed between the first interconnect wiring and the second interconnect wiring; and a conductive pad disposed on the interconnect structure, wherein the conductive pad is electrically connected to the conduction via, wherein the conduction via and the at least one stress release via are embedded in the first dielectric layer, and the conduction via is electrically insulated from the at least one stress release via. ### Claim 19 (depends on 18) The semiconductor die of claim 18, further comprising: a conductive bump disposed on the interconnect structure, wherein the conductive bump comprises a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via; and an insulating layer and a metallization pattern embedded in the insulating layer disposed between the interconnect structure and the conductive bump, wherein the conduction via and the at least one stress release via are disposed under the base portion of the conductive bump. ### Claim 20 (depends on 19) The semiconductor die of claim 19, further comprising a first passivation layer disposed on the metallization pattern and a second passivation layer disposed on the first passivation layer, and the conductive pad is embedded in the second passivation layer.