# US 12,009,325 B2 · Semiconductor device and electronic system including the same

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- Number: US 12,009,325 B2
- Document ID: US12009325B2
- Status: Granted
- Kind: B2
- Application number: 17/328,176
- Filed: 2021-05-24
- Published: 2022-05-05
- Granted: 2024-06-11
- Earliest claimed: 2020-11-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sung-Min Hwang; Jiwon Kim; Jaeho Ahn; Joon-Sung Lim; Sukkang Sung
- Web page: https://patentgrep.com/patent/US12009325B2

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 72/01931: {using blanket deposition}
- H10W 72/01953: {by etching}
- H10W 72/075: {of bond wires}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/551: {Materials of bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 80/031: {Changing or setting shapes of the pads}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 80/732: {having shape changed during the connecting}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/791: {of direct-bonded pads}
- H10W 90/792: {between multiple chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

## Claims

### Claim 1

A semiconductor device, comprising a cell structure stacked on a peripheral circuit structure, wherein:
the cell structure includes:
a plurality of gate electrode layers stacked on a first substrate;
a plurality of channel regions vertically penetrating the gate electrode layers;
a first interlayer dielectric layer on the first substrate and covering the gate electrode layers and the channel regions; and
a plurality of first metal pads exposed at the first interlayer dielectric layer and connected to the gate electrode layers and the channel regions,
the peripheral circuit structure includes:
at least one transistor on a second substrate;
a second interlayer dielectric layer on the second substrate and covering the transistor; and
a plurality of second metal pads exposed at the second interlayer dielectric layer and connected to the transistor,
the plurality of first metal pads include at least one first sub-pad and at least one second sub-pad that are adjacent to each other,
the plurality of second metal pads include at least one third sub-pad and at least one fourth sub-pad that are adjacent to each other,
the at least one first sub-pad and the at least one third sub-pad are coupled to each other, and a width of the at least one first sub-pad is greater than a width of the at least one third sub-pad,
the at least one second sub-pad and the at least one fourth sub-pad are coupled to each other, and a width of the at least one fourth sub-pad is greater than a width of the at least one second sub-pad,
a distance between a lateral surface of the at least one first sub-pad and a lateral surface of the at least one second sub-pad adjacent to the at least one first sub-pad is substantially the same as a distance between a lateral surface of the at least one third sub-pad and a lateral surface of the at least one fourth sub-pad adjacent to the at least one third sub-pad, and
the width of the at least one first sub-pad is substantially the same as the width of the at least one fourth sub-pad, and the width of the at least one second sub-pad is substantially the same as the width of the at least one third sub-pad.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein, at an interface between the first interlayer dielectric layer and the second interlayer dielectric layer:
an area of the at least one first sub-pad is greater than an area of the at least one third sub-pad such that, when viewed in a plan view, the at least one third sub-pad is in an inside of the at least one first sub-pad, and
an area of the at least one fourth sub-pad is greater than an area of the at least one second sub-pad, and when viewed in a plan, the at least one second sub-pad is in an inside of the at least one fourth sub-pad.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the at least one first sub-pad includes a plurality of first sub-pads, the at least one second sub-pad includes a plurality of second sub-pads, the at least one third sub-pad includes a plurality of third sub-pads, and the at least one fourth sub-pad includes a plurality of fourth sub-pads, and
the plurality of first sub-pads and the plurality of second sub-pads are alternately arranged in one direction parallel to a top surface of the first substrate.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the at least one first sub-pad includes a plurality of first sub-pads, the at least one second sub-pad includes a plurality of second sub-pads, the at least one third sub-pad includes a plurality of third sub-pads, and the at least one fourth sub-pad includes a plurality of fourth sub-pads,
the plurality of first sub-pads are on a first region of the first substrate, and
the plurality of second sub-pads are on a second region of the first substrate.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein,
the plurality of first metal pads further include a fifth sub-pad between the at least one first sub-pad and the at least one second sub-pad,
the plurality of second metal pads further include a sixth sub-pad between the at least one third sub-pad and the at least one fourth sub-pad,
the fifth sub-pad is coupled to the sixth sub-pad, and
a width of the fifth sub-pad is the same as a width of the sixth sub-pad.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the fifth sub-pad and the sixth sub-pad are vertically aligned with each other.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, wherein, at an interface between the first interlayer dielectric layer and the second interlayer dielectric layer:
the at least one first sub-pad and the at least one third sub-pad constitute a single body formed of the same material, and
the at least one second sub-pad and the at least one fourth sub-pad constitute a single body formed of the same material.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein:
the width of the at least one first sub-pad is greater than the width of the at least one second sub-pad, and
the width of the at least one third sub-pad is less than the width of the at least one fourth sub-pad.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the cell structure further includes a memory cell array, the memory cell array including:
a plurality of cell strings including a plurality of memory cells;
a plurality of word lines connected to the plurality of memory cells;
a plurality of bit lines connected to one side of the plurality of cell strings; and
a ground selection line connected to the plurality of cell strings.

### Claim 10 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the distance between the lateral surface of the at least one first sub-pad and the lateral surface of the at least one second sub-pad adjacent to the at least one first sub-pad is about 0.1 μm to about 10 μm.