# US 12,009,322 B2 · Package structure with through-via in molding compound and dielectric layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,322 B2
- Document ID: US12009322B2
- Status: Granted
- Kind: B2
- Application number: 17/670,481
- Filed: 2022-02-13
- Published: 2022-05-26
- Granted: 2024-06-11
- Earliest claimed: 2017-03-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Hsuan Tai; Ting-Ting Kuo; Yu-Chih Huang; Chih-Wei Lin; Hsiu-Jen Lin; Chih-Hua Chen; Ming-Da Cheng; Ching-Hua Hsieh; Hao-Yi Tsai; Chung-Shi Liu
- Web page: https://patentgrep.com/patent/US12009322B2

## CPC

- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/0198: {batch processes}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/655: Fan-out layouts
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

## Claims

### Claim 1

A package structure, comprising:
a semiconductor device;
a molding compound around the semiconductor device;
a first dielectric layer over the molding compound and the semiconductor device;
a through-via in the molding compound and the first dielectric layer;
a first redistribution line over the first dielectric layer and the through-via, wherein the first dielectric layer has an inner sidewall in contact with the first redistribution line and the through-via, a top end of the through-via is lower than a top surface of the first dielectric layer, and an entirety of a sidewall of the through-via higher than the molding compound is in contact with the inner sidewall of the first dielectric layer;
a second dielectric layer below the molding compound and the semiconductor device; and
a second redistribution line in the second dielectric layer, wherein the through-via has a bottom in contact with a topmost position of the second redistribution line.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the top end of the through-via is higher than a top of the molding compound.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the top end of the through-via is higher than a bottom of the first dielectric layer.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the sidewall of the through-via is in contact with the molding compound and the first dielectric layer.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein a bottom of the through-via is lower than a bottom of the molding compound.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein the molding compound has a portion between the through-via and the semiconductor device.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein a height of the through-via is greater than a thickness of the molding compound.

### Claim 8 (depends on 1)

The package structure of claim 1, wherein a height of the through-via is greater than a thickness of the semiconductor device.

### Claim 9 (depends on 1)

The package structure of claim 1, wherein a bottom of the first redistribution line is lower than the top surface of the first dielectric layer and higher than a bottom of the first dielectric layer.

### Claim 10

A package structure, comprising:
a first dielectric layer;
a first redistribution line in the first dielectric layer;
a semiconductor device over the first dielectric layer;
a molding compound around the semiconductor device and over the first dielectric layer;
a through-via in the first dielectric layer and the molding compound, wherein the first dielectric layer has an inner sidewall in contact with the through-via, and the through-via has a bottom in contact with a topmost position of the first redistribution line;
a second dielectric layer over the molding compound and the semiconductor device, wherein an entirety of a sidewall of the through-via higher than the molding compound is in contact with an inner sidewall of the second dielectric layer; and
a second redistribution line over the second dielectric layer and over the through-via.

### Claim 11 (depends on 10)

The package structure of claim 10, wherein the sidewall of the through-via is in contact with the first dielectric layer, the molding compound, and the second dielectric layer.

### Claim 12 (depends on 10)

The package structure of claim 10, further comprising:
a third dielectric layer over the second dielectric layer and the second redistribution line.

### Claim 13 (depends on 10)

The package structure of claim 10, further comprising:
a solder bump electrically connected to the first redistribution line.

### Claim 14 (depends on 10)

The package structure of claim 10, wherein the bottom of the through-via is level with the topmost position of the first redistribution line.

### Claim 15 (depends on 10)

The package structure of claim 10, wherein a bottommost position of the first redistribution line is higher than a bottom surface of the first dielectric layer.

### Claim 16

A package structure, comprising:
a semiconductor device;
a molding compound around the semiconductor device;
a first dielectric layer below the molding compound;
a redistribution line in the first dielectric layer;
a second dielectric layer over the molding compound; and
a through-via in the molding compound and extending beyond an entire height of the molding compound, wherein a top end of the through-via is lower than a top surface of the second dielectric layer, the through-via has a bottom in contact with a topmost position of the redistribution line, and an entirety of a sidewall of the through-via higher than the molding compound is in contact with an inner sidewall of the second dielectric layer.

### Claim 17 (depends on 16)

The package structure of claim 16, wherein the sidewall of the through via extends from the first dielectric layer to the second dielectric layer.

### Claim 18 (depends on 16)

The package structure of claim 16, wherein the through-via tapers towards the first dielectric layer.

### Claim 19 (depends on 16)

The package structure of claim 16, wherein the first dielectric layer has a portion between the through-via and the redistribution line.

### Claim 20 (depends on 16)

The package structure of claim 16, wherein the molding compound has a portion between the through-via and the first dielectric layer.