# US 12,009,319 B2 · Integrated circuit with metal stop ring outside the scribe seal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,319 B2 - Document ID: US12009319B2 - Status: Granted - Kind: B2 - Application number: 16/737,237 - Filed: 2020-01-08 - Published: 2021-07-08 - Granted: 2024-06-11 - Earliest claimed: 2020-01-08 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Christopher Daniel Manack; Qiao Chen; Michael Todd Wyant; Matthew John Sherbin; Patrick Francis Thompson - Web page: https://patentgrep.com/patent/US12009319B2 ## CPC - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 74/014: {using batch processing} - H10W 20/43: Layouts of interconnections - H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap. ## Claims ### Claim 1 An integrated circuit (IC) die, comprising: a substrate having a semiconductor surface layer with circuitry configured for at least one function including a plurality of metal interconnect levels thereon comprising a top metal interconnect level and a bottom metal interconnect level, with a passivation layer comprising a dielectric material on the top metal interconnect level; a scribe street around a periphery of the IC die, the scribe street comprising: a scribe seal utilizing at least two of the plurality of metal interconnect levels; an inner metal meander stop ring comprising at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap, and an outer metal meander stop ring comprising at least the top metal interconnect level located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap. ### Claim 2 (depends on 1) The IC die of claim 1, wherein the inner metal meander stop ring and the outer metal meander stop ring are both continuous encircling rings. ### Claim 3 (depends on 1) The IC die of claim 1, wherein the inner metal meander stop ring and the outer metal meander stop ring are both non-continuous rings, wherein the inner metal meander stop ring has a first plurality of segments and the outer metal meander stop ring has a second plurality of segments, wherein the first plurality of segments are positioned over gaps between the second plurality of segments, and wherein the second plurality of segments are positioned over gaps between the first plurality of segments. ### Claim 4 (depends on 1) The IC die of claim 1, wherein the inner metal meander stop ring and the outer metal meander stop ring further comprise at least one of the plurality of metal interconnect levels besides the top metal interconnect level. ### Claim 5 (depends on 1) The IC die of claim 1, wherein the inner metal meander stop ring and the outer metal stop rings are both 1 μm to 3 μm wide. ### Claim 6 (depends on 1) The IC die of claim 1, wherein the inner metal meander stop ring and the outer metal meander stop rings are substantially parallel to one another and are exclusively along the periphery of the IC die. ### Claim 7 An integrated circuit (IC) die, comprising: a substrate having a semiconductor surface layer with circuitry configured for at least one function including a plurality of metal interconnect levels thereon including at least four metal interconnect levels comprising a top metal interconnect level and a bottom metal interconnect level, with a passivation layer comprising a dielectric material on the top metal interconnect level; a scribe street around a periphery of the IC die, the scribe street comprising: a scribe seal utilizing at least two of the plurality of metal interconnect levels, and a single metal meander stop ring located outside the scribe seal consisting of the top metal interconnect level and at most a metal interconnect level immediately below the top metal interconnect layer, wherein the scribe seal and the single metal meander stop ring are separated by a separation gap. ### Claim 8 (depends on 7) The IC die of claim 7, wherein the single metal meander stop ring consists of only the top metal interconnect level. ### Claim 9 (depends on 7) The IC die of claim 7, wherein the single metal meander stop ring comprises a continuous encircling ring. ### Claim 10 A method of fabricating integrated circuit (IC) die, comprising: providing a substrate having a semiconductor surface layer with a plurality of the IC die each having circuitry in the semiconductor surface layer configured for at least one function, with a scribe street positioned between adjacent ones of the plurality of IC die; forming a metal stack including a plurality of metal interconnect levels thereon comprising a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level, the forming the plurality of metal interconnect levels including: forming in the scribe street a scribe seal around a periphery of the plurality of IC die utilizing at least two of the plurality of metal interconnect levels, forming an inner metal meander stop ring utilizing the top metal interconnect level and an outer metal meander stop ring outside the scribe seal, wherein the inner metal meander stop ring is separated from the scribe seal by a first separation gap, and wherein the outer metal meander stop ring is separated from the inner metal meander stop ring by a second separation gap. ### Claim 11 (depends on 10) The method of claim 10, further comprising etching the passivation layer in a portion of the scribe street between adjacent ones of the outer metal meander stop rings to provide a trench in the passivation layer. ### Claim 12 (depends on 10) The method of claim 10, further comprising stealth laser dicing focused depthwise in the scribe street to generate embedded crystal damage in the scribe street. ### Claim 13 (depends on 10) The method of claim 10, wherein the inner metal meander stop ring and the outer metal stop rings are both 1 μm to 3 μm wide. ### Claim 14 (depends on 10) The method of claim 10, wherein the inner metal meander stop ring and the outer metal meander stop ring are both non-continuous rings, wherein the inner metal meander stop ring has a first plurality of segments and the outer metal meander stop ring has a second plurality of segments, wherein the first plurality of segments are positioned over gaps between the second plurality of segments, and wherein the second plurality of segments are positioned over gaps between the first plurality of segments. ### Claim 15 A method of fabricating integrated circuit (IC) die, comprising: providing a substrate having a semiconductor surface layer with a plurality of the IC die each having circuitry in the semiconductor surface layer configured for at least one function, with a scribe street positioned between adjacent ones of the plurality of IC die; forming a metal stack including a plurality of metal interconnect levels including at least four levels thereon comprising a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level, the forming the plurality of metal interconnect levels including: forming in the scribe street a scribe seal around a periphery of the plurality of IC die utilizing at least two of the plurality of metal interconnect levels, and forming a single metal meander stop ring outside the scribe seal that is separated from the scribe seal by a separation gap, the single metal meander stop ring consisting of the top metal interconnect level and at most a metal interconnect level immediately below the top metal interconnect layer. ### Claim 16 (depends on 15) The method of claim 15, wherein the single metal meander stop ring consists of only the top metal interconnect level. ### Claim 17 (depends on 15) The method of claim 15, further comprising stealth laser dicing focused depthwise in the scribe street of the substrate to generate embedded crystal damage in the scribe street. ### Claim 18 (depends on 15) The method of claim 15, wherein the single metal meander stop ring is 1 μm to 3 μm wide. ### Claim 19 (depends on 15) The method of claim 15, wherein the single meander stop ring is a continuous encircling ring that encircles the IC die.