# US 12,009,318 B2 · Control of warpage using ABF GC cavity for embedded die package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,318 B2 - Document ID: US12009318B2 - Status: Granted - Kind: B2 - Application number: 17/714,944 - Filed: 2022-04-06 - Published: 2022-07-21 - Granted: 2024-06-11 - Earliest claimed: 2014-09-19 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Digvijay A. Raorane; Ian En Yoon Chin; Daniel N. Sobieski - Web page: https://patentgrep.com/patent/US12009318B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/685: comprising multiple insulating layers - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material. ## Claims ### Claim 1 A semiconductor package, comprising: a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall; a plurality of conductive contacts at the second side of the die; a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die; a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts; a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts; a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via; a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the reinforcement layer has a CTE less than a CTE of the dielectric material. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the reinforcement layer has a surface co-planar with the second side of the die. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the reinforcement layer has a surface above the first side of the die. ### Claim 5 (depends on 1) The semiconductor package of claim 1, further comprising a die attach film on the first side of the die. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the reinforcement layer completely laterally surrounds the die. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the first solder bump is coupled to the first conductive trace by a third conductive trace. ### Claim 8 (depends on 6) The semiconductor package of claim 6, wherein the second solder bump is coupled to the second conductive trace by a fourth conductive trace. ### Claim 9 A semiconductor package, comprising: a die having a first side and a second side opposite the first side, the die having a first lateral sidewall and a second lateral sidewall, and the die having electronic circuitry on the second side of the die; a plurality of conductive contacts electrically coupled to the electronic circuitry of the die; a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die; a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts; a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts; a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via; a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein the reinforcement layer has a CTE less than a CTE of the dielectric material. ### Claim 11 (depends on 9) The semiconductor package of claim 9, wherein the reinforcement layer has a surface co-planar with the second side of the die. ### Claim 12 (depends on 9) The semiconductor package of claim 9, wherein the reinforcement layer has a surface above the first side of the die. ### Claim 13 (depends on 9) The semiconductor package of claim 9, further comprising a die attach film on the first side of the die. ### Claim 14 (depends on 9) The semiconductor package of claim 9, wherein the reinforcement layer completely laterally surrounds the die. ### Claim 15 (depends on 9) The semiconductor package of claim 9, wherein the first solder bump is coupled to the first conductive trace by a third conductive trace. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein the second solder bump is coupled to the second conductive trace by a fourth conductive trace. ### Claim 17 A semiconductor package, comprising: a die having a first side and a second side opposite the first side, and the die having a first lateral sidewall and a second lateral sidewall; a plurality of conductive contacts at the second side of the die; a reinforcement layer having a first portion laterally adjacent to and in contact with the first lateral sidewall of the die, the reinforcement layer having a second portion laterally adjacent to and in contact with the second lateral sidewall of the die, and the reinforcement layer having a thickness less than a thickness of the die; a dielectric material on and in direct physical contact with the second side of the die and on the surface of the reinforcement layer; a first conductive via through the dielectric material, the first conductive via coupled to a first of the plurality of conductive contacts; a second conductive via through the dielectric material, the second conductive via coupled to a second of the plurality of conductive contacts; a first conductive trace on the dielectric material, the first conductive trace in contact with the first conductive via; a second conductive trace on the dielectric material, the second conductive trace in contact with the second conductive via; a first solder bump electrically coupled to the first conductive trace, the first solder bump outside of a periphery of the die and inside a periphery of the reinforcement layer, wherein the first conductive trace extends from inside the periphery of the die to a location vertically over the first solder bump; and a second solder bump electrically coupled to the second conductive trace, the second solder bump outside of the periphery of the die and inside the periphery of the reinforcement layer, wherein the second conductive trace extends from inside the periphery of the die to a location vertically over the second solder bump, and wherein there are no solder bumps inside of the periphery of the die. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein the reinforcement layer has a CTE less than a CTE of the dielectric material. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the reinforcement layer has a surface co-planar with the second side of the die. ### Claim 20 (depends on 17) The semiconductor package of claim 17, wherein the reinforcement layer has a surface above the first side of the die. ### Claim 21 (depends on 17) The semiconductor package of claim 17, wherein the reinforcement layer completely laterally surrounds the die. ### Claim 22 (depends on 17) The semiconductor package of claim 17, wherein the first solder bump is electrically coupled to the first conductive trace by a third conductive trace, and wherein the second solder bump is electrically coupled to the second conductive trace by a fourth conductive trace. ### Claim 23 (depends on 17) The semiconductor package of claim 17, further comprising a die attach film on the first side of the die.