# US 12,009,317 B2 · Semiconductor package structure and method for manufacturing the same

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- Number: US 12,009,317 B2
- Document ID: US12009317B2
- Status: Granted
- Kind: B2
- Application number: 17/321,139
- Filed: 2021-05-14
- Published: 2022-11-17
- Granted: 2024-06-11
- Earliest claimed: 2021-05-14
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: You-Lung Yen; Bernd Karl Appelt; Kay Stefan Essig
- Web page: https://patentgrep.com/patent/US12009317B2

## CPC

- H10W 40/778: {in encapsulations}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 40/77: Auxiliary members characterised by their shape
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/453: {comprising flexible metallic tapes}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 74/01: Manufacture or treatment
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

## Claims

### Claim 1

A semiconductor package structure, comprising:
a substrate;
a semiconductor device disposed over the substrate;
an encapsulant encapsulating the semiconductor device;
a balance structure over the semiconductor device and contacting the encapsulant; and
a warpage-resistant layer between the semiconductor device and the balance structure, wherein the warpage-resistance layer comprises a metal layer,
wherein the balance structure comprises a metal material directly contacting the warpage-resistant layer; and
wherein the warpage-resistant layer comprises a microstructure on a surface contacting the balance structure.

### Claim 2 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the warpage-resistant layer comprises titanium/copper.

### Claim 3 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the balance structure is entirely above the warpage-resistant layer.

### Claim 4 (depends on 3)

The semiconductor package structure as claimed in claim 3, wherein a lateral surface of the balance structure substantially aligns to a lateral surface of the warpage-resistance layer and a lateral surface of the semiconductor device.

### Claim 5 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein a bottommost surface of the balance structure directly contacts a topmost surface of the warpage-resistant layer.

### Claim 6 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the balance structure is entirely above the warpage-resistant layer, and a bottommost surface of the balance structure directly contacts a topmost surface of the warpage-resistant layer.

### Claim 7 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein a peripheral outline of the balance structure overlaps a peripheral outline of the substrate from a top view perspective.

### Claim 8

A semiconductor package structure, comprising:
a substrate;
a semiconductor device disposed over the substrate;
an encapsulant encapsulating the semiconductor device;
a balance structure over the semiconductor device and contacting the encapsulant; and
a warpage-resistant layer between the semiconductor device and the balance structure, wherein the warpage-resistance layer comprises a metal layer,
wherein a surface roughness of an upper surface of the balance structure is greater than a surface roughness of a bottom surface of the balance structure.

### Claim 9

A semiconductor package structure, comprising:
a substrate;
a semiconductor device disposed over the substrate;
an encapsulant encapsulating the semiconductor device;
a balance structure over the semiconductor device and contacting the encapsulant; and
a warpage-resistant layer between the semiconductor device and the balance structure, wherein the warpage-resistance layer comprises a metal layer,
wherein a surface roughness of an upper surface of the warpage-resistant layer is greater than a surface roughness of a bottom surface of the warpage-resistant layer.