# US 12,009,316 B2 · Semiconductor structure and method of manufacturing a semiconductor structure

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- Number: US 12,009,316 B2
- Document ID: US12009316B2
- Status: Granted
- Kind: B2
- Application number: 17/244,800
- Filed: 2021-04-29
- Published: 2022-11-03
- Granted: 2024-06-11
- Earliest claimed: 2021-04-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Hsien-Wen Liu; Hsien-Wei Chen; Jie Chen
- Web page: https://patentgrep.com/patent/US12009316B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 74/01: Manufacture or treatment
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10W 70/635: {Through-vias}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a first die having a first surface and a second surface opposite to the first surface, a conductive bump disposed at the first surface, and an RDL under the conductive bump. The RDL includes an interconnect structure and a dielectric layer, and the interconnect structure is electrically connected to the first die through the conductive bump. The semiconductor structure further includes a molding over the RDL and surrounding the first die and the conductive bump, an adhesive over the molding and the second surface, and a support element over the adhesive. A method includes providing a first die having a first surface and a second surface, a redistribution layer over the first surface, and a molding surrounding the first die; removing a portion of the molding to expose the second surface; and attaching a support element over the molding and the second surface.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first die having a first surface and a second surface opposite to the first surface;
a second die adjacent to the first die, wherein the second die includes a third surface and a fourth surface opposite to the third surface;
a first conductive bump disposed at the first surface of the first die and surrounded by a first underfill disposed under the first die;
a second conductive bump disposed at the third surface of the second die and surrounded by a second underfill disposed under the second die;
a redistribution layer (RDL) under the first conductive bump and the second conductive bump, and including an interconnect structure and a dielectric layer surrounding the interconnect structure, wherein the interconnect structure is electrically connected to the first die through the first conductive bump and the second die through the second conductive bump;
a molding over the RDL and surrounding the first die, the second die, the first conductive bump, the second conductive bump, the first underfill and the second underfill;
an adhesive over the molding, the second surface of the first die and the fourth surface of the second die; and
a support element over the adhesive,
wherein the molding is in contact with the first die, the second die, the first underfill and the second underfill,
a width of the molding is substantially greater than a width of the adhesive,
the width of the molding is substantially greater than a width of the support element, and
a portion of the molding is disposed between the first die and the second die and between the first conductive bump and the second conductive bump.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the support element extends laterally beyond an edge of the first die from a top view.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the width of the adhesive is substantially equal to the width of the support element.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein a width of the RDL is substantially equal to the width of the support element.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a thickness of the support element is substantially greater than a thickness of the first die.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein a ratio of a thickness of the first die to a thickness of the support element is between about 1:1.2 and about 1:10.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the molding is disposed between the adhesive and the dielectric layer of the RDL.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the portion of the molding contacts the adhesive, the first underfill, the second underfill, the first die and the second die.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the support element is disposed over the second surface of the first die and the fourth surface of the second die.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the support element extends laterally beyond edges of the first die and the second die from a top view.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein a sidewall of the adhesive is vertically aligned with a sidewall of the support element.

### Claim 12

A semiconductor structure, comprising:
a first die having a first surface and a second surface opposite to the first surface;
a second die adjacent to the first die and having a third surface and a fourth surface opposite to the third surface;
a redistribution layer (RDL) under the first surface of the first die and the third surface of the second die, and including an interconnect structure electrically connected to the first die and the second die;
a first conductive bump between the RDL and the first surface of the first die;
a second conductive bump between the RDL and the third surface of the second die;
a first underfill between the RDL and the first surface of the first die and surrounding the first conductive bump;
a second underfill between the RDL and the third surface of the second die and surrounding the second conductive bump;
a molding over the RDL and surrounding the first die and the second die;
an adhesive over the molding, the second surface of the first die and the fourth surface of the second die; and
a support element over the molding and the second surface of the first die and the fourth surface of the second die,
wherein at least a portion of the molding is disposed between the first underfill and the second underfill,
the portion of the molding is in contact with the first die, the second die, the first underfill and the second underfill,
a width of the molding is substantially greater than a width of the adhesive,
the width of the molding is substantially greater than a width of the support element, and
the width of the adhesive is substantially equal to the width of the support element.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the support element is in contact with the second surface of the first die.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein the support element is a dummy wafer or a silicon substrate.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, wherein the portion of the molding is disposed between the first die and the second die.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, further comprising:
a third die disposed under the RDL and electrically connected to the interconnect structure;
wherein a first portion of the third die overlaps a portion of the first die from a top view, and a second portion of the third die overlaps a portion of the second die from a top view.

### Claim 17

A semiconductor structure, comprising:
a redistribution layer (RDL) including an interconnect structure;
a support element over the RDL;
a first die having a first surface electrically connected to the interconnect structure and a second surface opposite to the first surface, wherein the first die is disposed between the RDL and the support element;
a second die having a third surface electrically connected to the interconnect structure and a fourth surface opposite to the third surface, wherein the second die is disposed between the RDL and the support element and adjacent to the first die;
a first underfill disposed under the first surface of the first die and above the RDL;
a second underfill disposed under the third surface of the second die and above the RDL; and
a molding surrounding the first die, the second die, the first underfill and the second underfill, and disposed between the RDL and the support element;
an adhesive between the support element and the molding,
wherein a portion of the molding is in contact with the first underfill, the second underfill, the first die and the second die,
a width of the molding is substantially greater than a width of the adhesive,
the width of the molding is substantially greater than a width of the support element, and
the width of the adhesive is substantially equal to the width of the support element.

### Claim 18 (depends on 17)

The semiconductor structure of claim 17, wherein the second surface of the first die is coplanar with a surface of the molding.

### Claim 19 (depends on 17)

The semiconductor structure of claim 17, wherein a portion of a top surface of the molding is exposed through the support element.

### Claim 20 (depends on 17)

The semiconductor structure of claim 17, further comprising:
a third die disposed under the RDL and electrically connected to the interconnect structure;
wherein a portion of the RDL is disposed between the first die and the third die, and a portion of the third die overlaps a portion of the first die.