# US 12,009,313 B2 · Semiconductor package shielding structure

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- Number: US 12,009,313 B2
- Document ID: US12009313B2
- Status: Granted
- Kind: B2
- Application number: 17/492,493
- Filed: 2021-10-01
- Published: 2023-04-06
- Granted: 2024-06-11
- Earliest claimed: 2021-10-01
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Meng-Jen Wang; Chien-Yuan Tseng; Hung Chen Kuo; Ying-Hao Wei; Chia-Feng Hsu; Yuan-Long Chiao
- Web page: https://patentgrep.com/patent/US12009313B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 44/248: {for antennas}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 90/00: Package configurations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.

## Claims

### Claim 1

A semiconductor package, comprising:
a substrate having a first face;
at least one first electronic component mounted adjacent to a first region of the first face;
a plurality of second electronic components mounted adjacent to a second region of the first face;
an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the at least one first electronic component, and wherein the encapsulant covers the plurality of second electronic components through a layer of conductive material;
an insulating material disposed over and between the plurality of second electronic components; and
a cap member over the plurality of second electronic components and in contact with the insulating material,
wherein the insulating material defines a lateral surface covered by the layer of conductive material,
wherein an upper border of the insulating material is higher than a bottom surface of the cap member.

### Claim 2 (depends on 1)

The semiconductor package of claim 1,
wherein the lateral surface defines a convex curved profile extending from a lateral surface of the cap member to the first face of the substrate in a lateral cross-section.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the cap member is kept at a standoff distance over the plurality of second electronic components without contacting the plurality of second electronic components.

### Claim 4

A semiconductor package, comprising:
a substrate having a first face;
at least one first electronic component mounted adjacent to a first region of the first face;
a plurality of second electronic components mounted adjacent to a second region of the first face;
an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the at least one first electronic component, and wherein the encapsulant covers the plurality of second electronic components through a layer of conductive material;
an insulating material disposed over and between the plurality of second electronic components; and
a cap member over the plurality of second electronic components and in contact with the insulating material,
wherein the layer of conductive material comprises a metallic film that provides substantially conformally coverage over a top surface of the cap member, a lateral surface of the cap member, and a portion of the first face of the substrate.

### Claim 5

The semiconductor package of 7,
wherein a thickness of the metallic film over the top surface of the cap member is greater than a thickness of the metallic film over the substrate, and
wherein the thickness of the metallic film over the substrate is greater than a thickness of the metallic film over the lateral surface of the cap member.