# US 12,009,312 B2 · Semiconductor device package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,312 B2 - Document ID: US12009312B2 - Status: Granted - Kind: B2 - Application number: 17/483,720 - Filed: 2021-09-23 - Published: 2023-03-23 - Granted: 2024-06-11 - Earliest claimed: 2021-09-23 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Chanyuan Liu; Kuo-Hsien Liao; Yu-Hsiang Sun - Web page: https://patentgrep.com/patent/US12009312B2 ## CPC - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 42/271: {the arrangements being between stacked chips} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 72/0198: {batch processes} - H10W 74/10: characterised by their shape or disposition - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/00: Package configurations - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a substrate having a first face and an opposing second face, wherein the first face is mounted with a first semiconductor component and a plurality of connectors; and a first shielding member covering the first semiconductor component and a first group of the plurality of connectors, while exposing a second group of the plurality of connectors. ## Claims ### Claim 1 A semiconductor package, comprising: a substrate having a first face and an opposing second face, wherein the first face is mounted with a first semiconductor component and a plurality of connectors; and a first shielding member covering the first semiconductor component and a first group of the plurality of connectors, while exposing a second group of the plurality of connectors, wherein the first semiconductor component is in physical contact with the first shielding member. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the first shielding member contacts each of the first group of the connectors. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the first shielding member and a second shielding member overlap each other. ### Claim 4 A semiconductor device, comprising: a circuit board having a plurality of conductive pads arranged on a mounting face thereof and a semiconductor package mounted over the circuit board, the semiconductor package comprising: a substrate having a first face arranged toward the mounting face of the circuit board, wherein the first face is mounted with a first semiconductor component and a plurality of connectors; a first shielding member extending between one of the plurality of conductive pads and one of the plurality of connectors; a first molding member encapsulating a second face opposite to the first face; and a second shielding member covering the second molding member, wherein the first shielding member and the second shielding member are physically separated. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the first shielding member comprises a first conductive material; wherein the second shielding member comprises a second conductive material different from the first conductive material. ### Claim 6 An electronic package, an electronic component; a plurality of electrical contacts configured to connect the electronic package to an external electronic device; and a shielding element configured to shield the electronic component from electromagnetic interference; wherein a first group of the electrical contacts is electrically connected to the shielding element and a second group of the electrical contacts is electrically dis-connected with the shielding element, wherein a bottom profile of the second group of the electrical contacts protrudingly exposes from the shielding element. ### Claim 7 (depends on 1) The semiconductor package of claim 1, further comprising: a molding member encapsulating the second face; and a second shielding member covering the molding member, wherein an upper periphery of the first shielding member has a highest boundary, wherein a lower periphery of the second shielding member has a lowest boundary, wherein the lowest boundary and the highest boundary are situated at different elevations. ### Claim 8 (depends on 7) The semiconductor package of claim 7, wherein the second shielding member and the first shielding member are physically separated. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the plurality of connectors are arranged around the first semiconductor component in a view over the first face, wherein the first shielding member has a plurality of notch profiles along an edge portion of the first shielding member, respectively adjacent to the exposed second group of the plurality of connectors. ### Claim 10 (depends on 4) The semiconductor device of claim 4, wherein the plurality of conductive pads of the circuit board includes at least a pad that projectively overlaps the first semiconductor component of the semiconductor package. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the first shielding member is in contact with one of the plurality of conductive pads through solder. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the solder between the first shielding member and the one of the plurality of conductive pads defines a first height; wherein one of the plurality of connectors exposed by the first shielding member defines a second height; wherein the second height is greater than the first height. ### Claim 13 (depends on 6) The electronic package of claim 6, wherein the shielding element encompasses the electronic component and the first group of the electrical contacts. ### Claim 14 (depends on 13) The electronic package of claim 13, wherein the shielding element exposes the second group of the electrical contacts. ### Claim 15 (depends on 6) The electronic package of claim 6, further comprising an encapsulant encapsulating the electronic component, wherein the shielding element disposed on an outer surface of the encapsulant and the electrical contacts are exposed from the outer surface of the encapsulant. ### Claim 16 (depends on 6) The electronic package of claim 6, wherein the shielding element contacts at least one of the first group of electrical contacts. ### Claim 17 (depends on 6) The electronic package of claim 6, wherein the shielding element is spaced apart from at least one of the second group of the electrical contacts.