# US 12,009,310 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,310 B2 - Document ID: US12009310B2 - Status: Granted - Kind: B2 - Application number: 17/565,067 - Filed: 2021-12-29 - Published: 2022-04-21 - Granted: 2024-06-11 - Earliest claimed: 2020-01-07 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Kenshi Terashima - Web page: https://patentgrep.com/patent/US12009310B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H05K 1/02: Details - H10W 70/611: {for connecting multiple chips together} - H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00} - H10W 72/071: {Connecting or disconnecting} - H10W 90/00: Package configurations - H10W 72/073: {of die-attach connectors} - H10W 72/07302: {using an auxiliary member} - H10W 72/075: {of bond wires} - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/381: {Auxiliary members} - H10W 72/387: {Flow barriers} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/5522: {comprising gold [Au]} - H10W 72/5524: {comprising aluminium [Al]} - H10W 72/5525: {comprising copper [Cu]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/735: {between a chip and a laterally-adjacent insulating package substrate, interposer or RDL} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A conductive plate includes a first slit formed in the space between a first chip area and a second chip area, a second slit formed in the space between the first chip area and a terminal area, and a third slit formed in the space between the second chip area and the terminal area. The first slit is a continuous line that penetrates through the conductive plate, whereas the second and third slits are continuous lines that do not penetrate through the conductive plate. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate including an insulating plate and a conductive plate disposed on a front surface of the insulating plate, the conductive plate having a first chip area, a second chip area and a terminal area in the front surface of the conductive plate; a first semiconductor chip disposed in the first chip area on the front surface of the conductive plate; a second semiconductor chip disposed in the second chip area on the front surface of the conductive plate; and a wiring terminal disposed in the terminal area on the front surface of the conductive plate, wherein the conductive plate includes, on the front surface thereof, a first slit extending in a space between the first chip area and the second chip area, a second slit extending in a space between the first chip area and the terminal area, and a third slit extending in a space between the second chip area and the terminal area, and wherein the first slit is provided as one continuous slit that penetrates completely through the conductive plate in a thickness direction orthogonal to direction of the front surface of the conductive plate and reaches the insulating plate, and one of the second slit and the third slit is provided as either one continuous slit that does not penetrate through the conductive plate in the thickness direction or a plurality of slits forming a broken line pattern, each of the plurality of slits penetrating completely through the conductive plate in the thickness direction and reaching the insulating plate. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein both the second and third slits are each provided as the one continuous slit that does not penetrate through the conductive plate in the thickness direction so that depths of the second and third slits are less than a thickness of the conductive plate. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second slit is provided along a side of the first semiconductor chip facing the terminal area in the conductive plate. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein a length of the second slit in a direction in which the second slit extends is approximately equal to a length of the side of the first semiconductor chip facing the terminal area. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the third slit is provided along a side of the second semiconductor chip facing the terminal area in the conductive plate. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein a length of the third slit in a direction in which the third slit extends is approximately equal to a length of the side of the second semiconductor chip facing the terminal area. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the second chip area includes a first side facing the first chip area across the first slit, and a second side perpendicular to the first side and facing the terminal area across the third slit. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the first chip area includes a third side that includes a first-third side and a second-third side, the first-third side facing the second chip area across the first slit, the second-third side facing the terminal area across the second slit. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the first chip area includes a third side facing the second chip area, and a fourth side perpendicular to the third side and facing the terminal area across the second slit. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are bonded to the conductive plate using a first bonding material, and the wiring terminal is bonded to the conductive plate using a second bonding material different from the first bonding material. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the first bonding material is a solder that contains a tin-antimony alloy as a main component, and the second bonding material is a solder that contains a tin-silver alloy as a main component. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein a width of the first slit in a direction orthogonal to a direction in which the first slit extends is approximately equal to a thickness of the first bonding material in the thickness direction. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are bonded to the conductive plate using a first bonding material, the wiring terminal is bonded to the conductive plate using a second bonding material, and a thickness of the first bonding material is less than a thickness of the second bonding material in the thickness direction. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the first semiconductor chip is a switching element, and the second semiconductor chip is a diode element.