# US 12,009,309 B2 · Semiconductor device having a plurality of semiconductor layers covering an emission layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,309 B2
- Document ID: US12009309B2
- Status: Granted
- Kind: B2
- Application number: 17/517,955
- Filed: 2021-11-03
- Published: 2022-05-26
- Granted: 2024-06-11
- Earliest claimed: 2020-11-20
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Ryuichi Oikawa
- Web page: https://patentgrep.com/patent/US12009309B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- G02B 6/4279: {Radio frequency signal propagation aspects of the electrical connection, high frequency adaptations}
- H01S 5/04256: {characterised by the configuration}
- H01S 5/4018: {Lasers electrically in series}
- H01S 5/4031: {Edge-emitting structures}
- H04B 10/40: Transceivers
- H04B 10/503: {Laser transmitters}
- H10W 70/611: {for connecting multiple chips together}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- G02B 6/421: {the intermediate optical component consisting of a short length of fibre, e.g. fibre stub}
- H01S 5/02212: Can-type, e.g. TO-CAN housings with emission along or parallel to symmetry axis
- H01S 5/02251: using optical fibres
- H01S 5/0234: Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
- H01S 5/02345: Wire-bonding
- H01S 5/026: Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06)
- H01S 5/12: the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers (comprising a photonic bandgap structure H01S5/11; surface-emitting lasers H01S5/18)
- H01S 5/227: Buried mesa structure {; Striped active layer}
- H01S 5/4043: {with vertically stacked active layers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H04B: TRANSMISSION

## Abstract

A first semiconductor element (laser diode) and a second semiconductor element (laser diode) are connected to each other in series between a wiring electrically connected to an anode of the first semiconductor element and a wiring electrically connected to a cathode of the second semiconductor element. In this case, each of the first semiconductor element and the second semiconductor element includes a laminated pattern having an emission layer and a plurality of semiconductor layers covering this laminated pattern.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip having a semiconductor substrate, a first semiconductor element formed on the semiconductor substrate, and a second semiconductor element formed on the semiconductor substrate;
a first wiring electrically connected to an anode of the first semiconductor element; and
a second wiring electrically connected to a cathode of the second semiconductor element,
wherein each of the first semiconductor element and the second semiconductor element includes:
a laminated pattern formed on the semiconductor substrate, the laminated pattern including a first end surface, a second end surface opposite the first end surface, a first side surface located between the first end surface and the second end surface, a second side surface located between the first end surface and the second end surface and opposite to the first side surface, and an upper surface;
a first semiconductor layer covering the first side surface of the laminated pattern;
a second semiconductor layer covering the second side surface of the laminated pattern; and
a third semiconductor layer covering the upper surface of the laminated pattern,
wherein the laminated pattern of each of the first semiconductor element and the second semiconductor element includes:
a fourth semiconductor layer of a first conductive type formed on the semiconductor substrate;
a fifth semiconductor layer of a second conductive type formed on the fourth semiconductor layer, the second conductive type being opposite to the first conductive type; and
an emission layer formed at a boundary surface between the fourth semiconductor layer and the fifth semiconductor layer,
wherein an index of refraction of each of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is smaller than an index of refraction of each of the fourth semiconductor layer and the fifth semiconductor layer, and
wherein the first semiconductor element and the second semiconductor element are connected to each other in series between the first wiring and the second wiring.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the semiconductor chip further includes:
a semiconductor region formed between the semiconductor substrate and each of the first semiconductor element and the second semiconductor element;
a third wiring formed on the third semiconductor layer of the first semiconductor element via a first insulating layer; and
a fourth wiring formed on the third semiconductor layer of the second semiconductor element via a second insulating layer so as to be in contact with the semiconductor region, and
wherein an anode of the second semiconductor element is electrically connected to a cathode of the first semiconductor element via the semiconductor region and the fourth wiring.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein the third wiring electrically connected to the anode of the first semiconductor element is electrically connected to the first wiring via a first bonding wire, and
wherein the semiconductor region electrically connected to the cathode of the second semiconductor element is electrically connected to the second wiring via a second bonding wire.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3,
wherein the laminated pattern is covered with each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer via a passivation film.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3,
wherein irregularities are formed in a region of the semiconductor substrate located directly under the laminated pattern so as to be in contact with the semiconductor region.

### Claim 6 (depends on 2)

The semiconductor device according to claim 2,
wherein the semiconductor substrate includes:
a main surface on which the laminated pattern of the first semiconductor element and the laminated pattern of the second semiconductor element are formed;
a back surface opposite to the main surface; and
a cathode electrode formed on the back surface,
wherein the third wiring electrically connected to the anode of the first semiconductor element is electrically connected to the first wiring via a first bonding wire, and
wherein the semiconductor region electrically connected to the cathode of the second semiconductor element is electrically connected to the second wiring via the cathode electrode.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6,
wherein the laminated pattern is covered with each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer via a passivation film.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6,
wherein irregularities are formed in a region of the semiconductor substrate located directly under the laminated pattern so as to be in contact with the semiconductor region.

### Claim 9

A semiconductor device comprising:
a first semiconductor chip having a first semiconductor substrate and a first semiconductor element formed on the first semiconductor substrate;
a second semiconductor chip having a second semiconductor substrate and a second semiconductor element formed on the second semiconductor substrate;
a first wiring electrically connected to an anode of the first semiconductor element; and
a second wiring electrically connected to a cathode of the second semiconductor element,
wherein the first semiconductor element includes:
a first laminated pattern formed on the first semiconductor substrate, the first laminated pattern including a first end surface, a second end surface opposite the first end surface, a first side surface located between the first end surface and the second end surface, a second side surface located between the first end surface and the second end surface and opposite to the first side surface, and a first upper surface;
a first semiconductor layer covering the first side surface of the first laminated pattern;
a second semiconductor layer covering the second side surface of the first laminated pattern; and
a third semiconductor layer covering the first upper surface of the first laminated pattern, wherein the second semiconductor element includes:
a second laminated pattern formed on the second semiconductor substrate, the second laminated pattern including a third end surface, a fourth end surface opposite the third end surface, a third side surface located between the third end surface and the fourth end surface, a fourth side surface located between the third end surface and the fourth end surface and opposite to the third side surface, and a third upper surface;
a fourth semiconductor layer covering the third side surface of the second laminated pattern;
a fifth semiconductor layer covering the fourth side surface of the second laminated pattern; and
a sixth semiconductor layer covering the first upper surface of the second laminated pattern,
wherein the first laminated pattern includes:
a seventh semiconductor layer of a first conductive type formed on the first semiconductor substrate;
an eighth semiconductor layer of a second conductive type formed on the seventh semiconductor layer, the second conductive type being opposite to the first conductive type; and
a first emission layer formed at a boundary surface between the seventh semiconductor layer and the eighth semiconductor layer,
wherein the second laminated pattern includes:
a ninth semiconductor layer of the first conductive type formed on the second semiconductor substrate;
a tenth semiconductor layer of the second conductive type formed on the ninth semiconductor layer; and
a second emission layer formed at a boundary surface between the ninth semiconductor layer and the tenth semiconductor layer,
wherein an index of refraction of each of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is smaller than an index of refraction of each of the seventh semiconductor layer and the eighth semiconductor layer,
wherein an index of refraction of each of the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer is smaller than an index of refraction of each of the ninth semiconductor layer and the tenth semiconductor layer, and
wherein the first semiconductor element and the second semiconductor element are connected to each other in series between the first wiring and the second wiring.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9,
wherein the first semiconductor chip further includes:
a first semiconductor region formed between the first semiconductor substrate and the first semiconductor element;
a third wiring formed on a first portion of the third semiconductor layer of the first semiconductor element via a first insulating layer; and
a fourth wiring formed on a second portion of the third semiconductor layer of the first semiconductor element via a second insulating layer so as to be in contact with the first semiconductor region,
wherein the second semiconductor chip further includes:
a second semiconductor region formed between the second semiconductor substrate and the second semiconductor element;
a fifth wiring formed on a first portion of the sixth semiconductor layer of the second semiconductor element via a third insulating layer; and
a sixth wiring formed on a second portion of the sixth semiconductor layer of the second semiconductor element via a fourth insulating layer so as to be in contact with the second semiconductor region, and
wherein an anode of the second semiconductor element is electrically connected to a cathode of the first semiconductor element via the first semiconductor region and a seventh wiring.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10,
wherein the third wiring electrically connected to the anode of the first semiconductor element is electrically connected to the first wiring via a first bonding wire, and
wherein the second semiconductor region electrically connected to the cathode of the second semiconductor element is electrically connected to the second wiring via a second bonding wire.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11,
wherein the first laminated pattern is covered with each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer via a first passivation film, and
wherein the second laminated pattern is covered with each of the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer via a second passivation film.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11,
wherein irregularities are formed in a region of the first semiconductor substrate located directly under the first laminated pattern so as to be in contact with the first semiconductor region, and
wherein irregularities are formed in a region of the second semiconductor substrate located directly under the second laminated pattern so as to be in contact with the second semiconductor region.

### Claim 14 (depends on 10)

The semiconductor device according to claim 10,
wherein the first semiconductor chip and the second semiconductor chip are arranged side by side, and
wherein the seventh wiring is a third bonding wire.

### Claim 15 (depends on 10)

The semiconductor device according to claim 10,
wherein the first semiconductor substrate includes:
a first main surface on which the first laminated pattern is formed;
a first back surface opposite to the first main surface; and
a first cathode electrode formed on the first back surface,
wherein the second semiconductor substrate includes:
a second main surface on which the second laminated pattern is formed;
a second back surface opposite to the second main surface; and
a second cathode electrode formed on the second back surface,
wherein the first semiconductor chip and the second semiconductor chip are arranged on the seventh wiring side by side,
wherein the second semiconductor chip is arranged so that an upper surface of the second semiconductor element faces an upper surface of the seventh wiring,
wherein the third wiring electrically connected to the anode of the first semiconductor element is electrically connected to the first wiring via a first bonding wire,
wherein a lower surface of the first cathode electrode is connected to the upper surface of the seventh wiring,
wherein an upper surface of the fifth wiring is connected to the upper surface of the seventh wiring, and
wherein the second semiconductor region electrically connected to the cathode of the second semiconductor element is electrically connected to the second wiring via the second cathode electrode and a second bonding wire.

### Claim 16 (depends on 10)

The semiconductor device according to claim 10,
wherein the first semiconductor substrate includes:
a first main surface on which the first laminated pattern is formed;
a first back surface opposite to the first main surface; and
a first cathode electrode formed on the first back surface, the first cathode electrode being the seventh wiring,
wherein the second semiconductor substrate includes:
a second main surface on which the second laminated pattern is formed;
a second back surface opposite to the second main surface; and
a second cathode electrode formed on the second back surface,
wherein the first semiconductor chip is arranged on the second semiconductor chip,
wherein the third wiring electrically connected to the anode of the first semiconductor element is electrically connected to the first wiring via a first bonding wire,
wherein a lower surface of the first cathode electrode is connected to an upper surface of the fifth wiring, and
wherein the second semiconductor region electrically connected to the cathode of the second semiconductor element is electrically connected to the second wiring via the second cathode electrode.

### Claim 17

An electronic device comprising:
a stem;
a dielectric substrate formed on the stem, the dielectric substrate having a first wiring and a second wiring arranged along the first wiring;
a first semiconductor chip mounted on the dielectric substrate, the first semiconductor chip having a semiconductor substrate, a first semiconductor element formed on the semiconductor substrate, and a second semiconductor element formed on the semiconductor substrate, an anode of the first semiconductor element being electrically connected to the first wiring, and a cathode of the second semiconductor element being electrically connected to the second wiring;
a mounting substrate coupled to the dielectric substrate via a flexible substrate; and
a second semiconductor chip mounted on the mounting substrate,
wherein each of the first semiconductor element and the second semiconductor element includes:
a laminated pattern formed on the semiconductor substrate, the laminated pattern including a first end surface, a second end surface opposite the first end surface, a first side surface located between the first end surface and the second end surface, a second side surface located between the first end surface and the second end surface and opposite to the first side surface, and an upper surface;
a first semiconductor layer covering the first side surface of the laminated pattern;
a second semiconductor layer covering the second side surface of the laminated pattern; and
a third semiconductor layer covering the upper surface of the laminated pattern,
wherein the laminated pattern of each of the first semiconductor element and the second semiconductor element includes:
a fourth semiconductor layer of a first conductive type formed on the semiconductor substrate;
a fifth semiconductor layer of a second conductive type formed on the fourth semiconductor layer, the second conductive type being opposite to the first conductive type; and
an emission layer formed at a boundary surface between the fourth semiconductor layer and the fifth semiconductor layer,
wherein an index of refraction of each of the first semiconductor layer, the second semiconductor layer and the third semiconductor layer is smaller than an index of refraction of each of the fourth semiconductor layer and the fifth semiconductor layer,
wherein the first semiconductor element and the second semiconductor element are connected to each other in series between the first wiring and the second wiring, and
wherein a driving circuit configured to drive the first semiconductor element and the second semiconductor element is provided in the second semiconductor chip.