# US 12,009,307 B2 · Multi-die FPGA implementing built-in analog circuit using active silicon connection layer

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- Number: US 12,009,307 B2
- Document ID: US12009307B2
- Status: Granted
- Kind: B2
- Application number: 17/421,460
- Filed: 2020-12-30
- Published: 2022-10-27
- Granted: 2024-06-11
- Earliest claimed: 2020-07-01
- Assignees: Wuxi Esiontech Co., Ltd.
- Applicants: Wuxi Esiontech Co., Ltd.
- Inventors: Yueer Shan; Yanfeng Xu; Jicong Fan; Yanfei Zhang; Hua Yan
- Web page: https://patentgrep.com/patent/US12009307B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/17744: {for input/output signals}
- H03K 19/1776: for memories
- H03K 19/17764: for reliability
- H03K 19/17796: for physical disposition of blocks
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses}
- H10W 90/00: Package configurations
- H10W 44/223: {Differential pair signal lines}
- H10W 44/234: {Arrangements for impedance matching}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/07254: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/9413: {on encapsulations}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

## Claims

### Claim 1

A multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, wherein the multi-die FPGA comprises a substrate, a silicon connection layer laminated on the substrate and a plurality of FPGA dies laminated on the silicon connection layer, the silicon connection layer covering all of the FPGA dies;
each FPGA die comprises a plurality of configurable functional modules, interconnection resource modules arranged around each of the configurable functional modules and connection point leads, the configurable functional modules within the FPGA die comprise at least a programmable logic block, a silicon stacked connection module and an input and output block, the silicon stacked connection module comprises a plurality of silicon stacked connection points, the programmable logic block within the FPGA die is connected to the silicon stack connection point and the input and output block respectively through the interconnection resource modules, the silicon stack connection points are connected to the corresponding connection point leads through top metal wires within a re-distribution layer; the connection point leads within each FPGA die are connected to the corresponding connection point leads in other FPGA dies through cross-die wires within the silicon connection layer, each FPGA die can be connected to any of the other FPGA dies through the cross-die wires within the silicon connection layer; the input and output block within the FPGA die is connected to the substrate through a silicon via within the silicon connection layer;
a first circuit structure is formed within the FPGA die, a port of the first circuit structure is connected to the corresponding silicon stack connection point via the interconnection resource module and then connected to the corresponding connection point lead through the top metal wire within the re-distribution layer;
a second circuit structure is laid out within the silicon connection layer, the second circuit structure comprises a plurality of analog circuit elements, the connection point leads within the FPGA die connected to the port of the first circuit structure is connected to a port of the second circuit structure through silicon connection layer wires within the silicon connection layer, the first circuit structure and the second circuit structure are connected to form a built-in analog circuit within the multi-die FPGA, the input and output block within the silicon connection layer is also connected to the substrate.

### Claim 2 (depends on 1)

The multi-die FPGA according to claim 1, wherein a circuit parameter specification of the second circuit structure is higher than a predetermined parameter specification which is the maximum circuit parameter specification achievable within the FPGA die for the same circuit structure.

### Claim 3 (depends on 2)

The multi-die FPGA according to claim 2, wherein the second circuit structure comprises a capacitor with a capacitance greater than a predetermined parameter specification for the capacitance which is the maximum capacitance achievable within the FPGA die, the capacitor having a uF-level or greater capacitance.

### Claim 4 (depends on 2)

The multi-die FPGA according to claim 2, wherein the second circuit structure comprises an inductor implemented by a winding within the silicon connection layer, the inductor having an inductance greater than a predetermined inductance parameter specification which is the maximum inductance achievable within the FPGA die, the inductor having an 100 nH-level or greater inductance.

### Claim 5 (depends on 1)

The multi-die FPGA according to claim 1, wherein the second circuit structure has a circuit size greater than a predetermined size.

### Claim 6 (depends on 5)

The multi-die FPGA according to claim 5, wherein the second circuit structure comprises at least one of a resistor, a bipolar transistor, an operational amplifier, a phase-locked loop, a delayed phase-locked loop, an oscillator, or an RF acquisition circuit.

### Claim 7 (depends on 1)

The multi-die FPGA according to claim 1, wherein the silicon connection layer and FPGA die use different process techniques, and the process technique used for the FPGA die is better than the process technique used for the silicon connection layer, the second circuit structure thus requiring a lower process level than a predetermined process level.

### Claim 8 (depends on 1)

The multi-die FPGA according to claim 1, wherein when analog signals are transmitted between the port of the first circuit structure and the port of the second circuit structure, the port of the first circuit structure is connected directly to the port of the second circuit structure through the silicon connection layer wire.

### Claim 9 (depends on 1)

The multi-die FPGA according to claim 1, wherein when digital signals are transmitted between the port of the first circuit structure and the port of the second circuit structure, a buffer is further provided on the silicon connection layer wire between the port of the first circuit structure and the port of the second circuit structure.

### Claim 10 (depends on 1)

The multi-die FPGA according to claim 1, wherein when differential signals are transmitted between the port of the first circuit structure and the port of the second circuit structure, the port of the first circuit structure comprises a first differential port and a second differential port, and the port of the second circuit structure also comprises a first differential port and a second differential port, the two first differential ports being connected in correspondence, the two second differential block being connected in correspondence, a signal wire between the two first differential ports and a signal wire between the two second differential port are identical.

### Claim 11 (depends on 1)

The multi-die FPGA according to claim 1, wherein the first circuit structure formed within at least one FPGA die of the multi-die FPGA is a digital circuit, and/or, the first circuit structure formed within at least one FPGA die is an analog circuit, and/or, the first circuit structure formed within at least one FPGA die is an analog-digital hybrid circuit.

### Claim 12 (depends on 1)

The multi-die FPGA according to claim 1, wherein the multi-die FPGA further comprises another die laminated on the silicon connection layer, a third circuit structure with an analog circuit structure is formed within the another die, a port of the third circuit structure is connected to the corresponding silicon stack connection points and then connected to the corresponding connection point leads through the top metal wires within the re-distribution layer and to a port of the second circuit structure through the silicon connection layer wires within the silicon connection layer; the third circuit structure is connected to the first circuit structure and the second circuit structure to form the built-in analog circuit within the multi-die FPGA.

### Claim 13 (depends on 1)

A multi-die FPGA according to claim 1, wherein a circuit parameter of the second circuit structure is regulated and configured by a configuring circuit within the multi-die FPGA.

### Claim 14 (depends on 13)

The multi-die FPGA according to claim 13, wherein the configuring circuit within the multi-die FPGA is a configuration chain within the FPGA die.

### Claim 15 (depends on 13)

The multi-die FPGA according to claim 13, wherein the configuring circuit within the multi-die FPGA is a dynamically reconfigurable port within the FPGA die.

### Claim 16 (depends on 1)

The multi-die FPGA according to claim 1, wherein the first circuit structure is built based on a programmable logic block within the FPGA die, the programmable logic block building the first circuit structure comprising at least one of a CLB, a BRAM and a DSP.

### Claim 17 (depends on 16)

The multi-die FPGA according to claim 16, wherein the programmable logic building the first circuit structure is dynamically configured by a dynamically programmable port of the FPGA die within which it is located.