# US 12,009,305 B2 · Semiconductor device and method for forming the same

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- Number: US 12,009,305 B2
- Document ID: US12009305B2
- Status: Granted
- Kind: B2
- Application number: 18/302,101
- Filed: 2023-04-18
- Published: 2023-09-07
- Granted: 2024-06-11
- Earliest claimed: 2020-04-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuo-Ju Chen; Chun-Hsien Huang; Su-Hao Liu; Liang-Yin Chen; Huicheng Chang; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12009305B2

## CPC

- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

## Claims

### Claim 1

A semiconductor device, comprising:
a first dielectric layer over a substrate and a conductive feature;
a second dielectric layer over the first dielectric layer;
a doped dielectric layer between the first dielectric layer and the second dielectric layer; and
a first metal structure in the first dielectric layer, the doped dielectric layer, and the second dielectric layer, wherein the first metal structure comprises:
a first metal portion in the first dielectric layer; and
a doped metal portion over the first metal portion, wherein the first metal portion and the doped metal portion comprise a same metal material, the doped dielectric layer and the doped metal portion comprise same dopants.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metal material comprises a noble metal material.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dopants comprise phosphorous (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first metal portion is a via between a metal line and the conductive feature.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the doped dielectric layer is in contact with the first dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer is disposed between the doped dielectric layer and the first dielectric layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a third dielectric layer between the first dielectric layer and the doped dielectric layer, wherein the third dielectric layer and the second dielectric layer comprise a same material.

### Claim 8

A semiconductor device, comprising:
a first dielectric layer over a substrate and a conductive feature;
a doped dielectric layer over the first dielectric layer;
a second dielectric layer over the doped dielectric layer; and
a first metal structure in the first dielectric layer, the doped dielectric layer, and the second dielectric layer, wherein the first metal structure comprises:
a first metal portion in the first dielectric layer;
a doped metal portion over the first metal portion, wherein the first metal portion and the doped metal portion comprise a same metal material, the doped dielectric layer and the doped metal portion comprise same dopants; and
a second metal portion over the doped metal portion, wherein the second metal portion is a same material as the first metal portion.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a third dielectric layer over the first dielectric layer, wherein the doped dielectric layer is over the third dielectric layer, wherein the third dielectric layer is a same dielectric material as the second dielectric layer.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials, wherein the doped dielectric layer contacts the first dielectric layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first metal structure is a via.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the dopants comprise phosphorous (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein a thickness of the doped metal portion is in range between 1 nm and 30 nm.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a thickness of the doped dielectric layer is in range between 1 nm and 50 nm.

### Claim 15

A semiconductor device, comprising:
a first dielectric layer over a substrate and a conductive feature;
a doped dielectric layer in the first dielectric layer, at least a portion of the first dielectric layer over the doped dielectric layer being undoped;
a first metal structure in the first dielectric layer and the doped dielectric layer, wherein the first metal structure comprises:
a first metal portion in the first dielectric layer; and
a doped metal portion over the first metal portion and in the doped dielectric layer, wherein the first metal portion and the doped metal portion comprise a same metal material, the doped dielectric layer and the doped metal portion comprise same dopants; and
a second dielectric layer over the doped dielectric layer; and
a second metal structure in the second dielectric layer, wherein the second metal structure contacts the first metal structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the dopants comprise phosphorous (P), boron (B), arsenic (As), gallium (Ga), or indium (In).

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the first metal structure is a via and the second metal structure is a line.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the doped dielectric layer extends to a bottom of the first dielectric layer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising a second metal portion over the first metal portion, wherein an upper surface of the second metal portion is level with an upper surface of the first dielectric layer.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the doped dielectric layer and the doped metal portion are substantially aligned with each other.