# US 12,009,304 B2 · Integrated circuit and method for forming the same

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- Number: US 12,009,304 B2
- Document ID: US12009304B2
- Status: Granted
- Kind: B2
- Application number: 18/334,136
- Filed: 2023-06-13
- Published: 2023-10-12
- Granted: 2024-06-11
- Earliest claimed: 2020-04-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Liang Chen; Li-Chun Tien
- Web page: https://patentgrep.com/patent/US12009304B2

## CPC

- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10W 20/427: {Power or ground buses}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 14/3462: {Nanowires}
- H10P 50/642: {Chemical etching}
- H10P 52/402: {of semiconductor materials}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a gate structure extending along a first direction parallel with a front-side surface of the substrate;
source/drain structures on opposite sides of the gate structure;
a backside via extending along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, wherein the backside via further comprises
a first portion extending between the two source/drain structures along the first direction, the first portion having a first width W1 in the first direction and
a second portion extending between two gate structures along the first direction, the second portion of the backside via having a second width W2 in the first direction, wherein the first width and the second width satisfy a first expression W1>W2; and
a power rail on a backside surface of the substrate and in contact with the backside via wherein the power rail has a third width W3 along the first direction and wherein the third width and the first width satisfy a second expression W3>W1.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a dielectric layer below the gate structure, wherein the first portion of the backside via is in contact with a side surface of the dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first dielectric spacer, wherein the first dielectric spacer comprises a horizontal portion in contact with a top surface of the first portion of the backside via and a vertical portion in contact with a first sidewall of the first portion of the backside via.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein:
the power rail is in contact with a bottom surface of the vertical portion of the first dielectric spacer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first dielectric spacer having a first vertical portion in contact with a first sidewall of the first portion of the backside via and a second vertical portion in contact with a second sidewall of the first portion of the backside via.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first dielectric spacer on a top surface of the second portion of the backside via; and
a second dielectric spacer arranged between a sidewall of the backside via and a sidewall of the first dielectric spacer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein:
the gate structure is in contact with a top surface of the second dielectric spacer.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein:
the power rail is in contact with a bottom surface of the second dielectric spacer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising:
a plurality of nanosheets arranged in a stacked structure;
a gate structure surrounding and separating each of the nanosheets;
a gate spacer above the nanosheets and on a sidewall of the gate structure;
semiconductor layers arranged vertically below the gate spacer, wherein each of the semiconductor layers is positioned between an adjacent pair of the nanosheets, and wherein the backside via further comprises a third portion, wherein the third portion is aligned with the semiconductor layers along the first direction; and
first, second, and third dielectric spacers arranged between the semiconductor layers and the third portion of the backside via.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein:
the gate spacer is in contact with
a top surface of the first dielectric spacer;
a top surface of the second dielectric spacer; and
a sidewall of the third dielectric spacer.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
forming a stack structure, the stack structure comprising alternating source and drain layers above a substrate;
etching the stack structure to form a trench;
forming a first dielectric spacer lining a sidewall surface of the trench;
forming a backside via in the trench;
forming a gate structure extending across the first dielectric spacer and the backside via;
after forming the gate structure, removing an interior portion of the first dielectric spacer not covered by the gate structure to form a first recess; and
filling the first recess with a first conductive material to increase a width of the backside via.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
performing a CMP process to a backside of the substrate until a bottom surface of the backside via is exposed; and
forming a metal line on the bottom surface of the backside via.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
after forming the backside via, etching back the backside via;
forming a first dielectric cap over the backside via, wherein the first dielectric cap and the first dielectric spacer comprise a first material; and
forming a second dielectric cap over the first dielectric cap, wherein the second dielectric cap comprises a second material, wherein the second material is different than the first material.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
forming a dielectric cap over the first conductive material before etching the interior portion of the first dielectric spacer.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
replacing the gate structure with a metal gate structure after enlarging the backside via.

### Claim 16

A method of manufacturing a semiconductor device, comprising:
forming a first epitaxial stack of alternating first semiconductor layers and second semiconductor layers over a front-side surface of a substrate;
forming a second epitaxial stack of alternating first semiconductor layers and second semiconductor layers over the front-side surface of the substrate;
forming a first dielectric spacer alongside a sidewall of the first and second epitaxial stacks;
filling a space between the sidewalls of the first and second epitaxial stacks with a sacrificial dielectric layer wherein the first dielectric spacers comprise a first material and the sacrificial dielectric layer comprises a second material;
performing a CMP process to a backside of the substrate until a bottom surface of the sacrificial dielectric layer is exposed;
removing the sacrificial dielectric layer to form a recess; and
filling the recess with a conductive material to form a backside via.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
prior to performing the CMP process to the backside of the substrate, etching back the sacrificial dielectric layer to form a first recess;
forming a first dielectric cap in the first recess and over the sacrificial dielectric layer, wherein the first dielectric cap and the first dielectric spacer are made of a first material; and
forming a second dielectric cap in the first recess and over the first dielectric cap, wherein the second dielectric cap is made of a second material.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
after forming the second dielectric cap, etching back the first dielectric spacer and second dielectric spacer;
removing the second dielectric spacer and the second dielectric cap to form a second recess between the sacrificial dielectric layer and the first dielectric spacer; and
filling the second recess with a dielectric material.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
forming a third dielectric cap in the second recess over the dielectric material filling the second recess, wherein the third dielectric cap and the first dielectric spacer are made of the first material.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
prior to filling the recess with the backside via, forming a silicide layer on an exposed sidewall of the first epitaxial stack and an exposed sidewall of the second epitaxial stack.