# US 12,009,301 B2 · Interconnect structure

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- Number: US 12,009,301 B2
- Document ID: US12009301B2
- Status: Granted
- Kind: B2
- Application number: 17/577,805
- Filed: 2022-01-18
- Published: 2022-05-05
- Granted: 2024-06-11
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shao-Kuan Lee; Cheng-Chin Lee; Hsin-Yen Huang; Hai-Ching Chen; Shau-Lin Shue
- Web page: https://patentgrep.com/patent/US12009301B2

## CPC

- H10P 14/6939: {characterised by the metal}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10P 14/61: using masks
- H10P 50/264: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/065: {by making at least a portion of the conductive part non-conductive, e.g. by oxidation}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.

## Claims

### Claim 1

An interconnect structure, comprising:
a first via in a first dielectric layer;
a first metal line on and electrically connected to the first via;
a first etching stop layer over the first dielectric layer;
a second metal line over the first etching stop layer;
an encapsulating layer including a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line;
a second dielectric layer nested within the encapsulating layer;
a second etching stop layer over and in contact with a top surface of the first vertical portion and a top surface of the second vertical portion of the encapsulating layer and a top surface of the second dielectric layer; and
a third etching stop layer over and in contact with a top surface of the second metal line.

### Claim 2 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the third etching stop layer extends along and is in contact with a sidewall and a top surface of the second etching stop layer.

### Claim 3 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the third etching stop layer partially covers a top surface of the first metal line.

### Claim 4 (depends on 1)

The interconnect structure as claimed in claim 1, further comprising:
a third dielectric layer over the third etching stop layer; and
a second via in the third dielectric layer and on the first metal line.

### Claim 5 (depends on 4)

The interconnect structure as claimed in claim 4, wherein the third dielectric layer includes a portion extending between the second etching stop layer and the second via.

### Claim 6 (depends on 1)

The interconnect structure as claimed in claim 1, further comprising:
a transistor over a substrate; and
a contact plug over a source/drain feature of the transistor, wherein the first via is on and electrically connected to the contact plug.

### Claim 7 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the first metal line comprises a metal bulk layer and a metal capping layer over the metal bulk layer, wherein the metal bulk layer and the metal capping layer are in contact with the first dielectric layer.

### Claim 8 (depends on 1)

The interconnect structure as claimed in claim 1, wherein the first etching stop layer is made of aluminum oxide, zirconium oxide, hafnium oxide, yttrium oxide, or hafnium oxide.

### Claim 9 (depends on 1)

The interconnect structure as claimed in claim 1, wherein a dielectric constant of the encapsulating layer is less than a dielectric constant of the first etching stop layer.

### Claim 10

An interconnect structure, comprising:
a first metal line and a second metal line in a first dielectric layer;
a first etching stop layer over the first metal line, the second metal line and the first dielectric layer, wherein the first etching stop layer includes a first portion directly above the second metal line and a second portion directly above the first dielectric layer, and the second portion of the first etching stop layer is thicker than the first portion of the first etching stop layer, and a bottom surface of the second portion of the first etching stop layer is substantially level to a bottom surface of the first portion of the first etching stop layer;
a second dielectric layer over the first etching stop layer;
a first via extending through the second dielectric layer and the first etching stop layer and landing on the first metal line;
a second etching stop layer below the second metal line and the first dielectric layer and surrounding a lower portion of the first metal line; and
an encapsulating layer including a first portion extending between the first metal line and the first dielectric layer, a second portion extending between the second metal line and the first dielectric layer and a third portion extending between the second etching stop layer and the first dielectric layer, wherein the encapsulating layer and the first dielectric layer are made of different materials.

### Claim 11 (depends on 10)

The interconnect structure as claimed in claim 10, wherein the dielectric constant of the first etching stop layer is greater than a dielectric constant of the second dielectric layer.

### Claim 12 (depends on 10)

The interconnect structure as claimed in claim 10, wherein the first via has a first bottom surface interfaced with the first metal line and a second bottom surface interfaced with the second portion of the first etching stop layer.

### Claim 13 (depends on 12)

The interconnect structure as claimed in claim 12, wherein the second bottom surface is located lower than a top surface of the second portion of the first etching stop layer.

### Claim 14 (depends on 10)

The interconnect structure as claimed in claim 10, wherein the first etching stop layer includes a third portion directly above the first metal line, the third portion of the first etching stop layer is thinner than the second portion of the first etching stop layer and in contact with the first via.

### Claim 15

An interconnect structure, comprising:
a first interconnect layer comprising a first via through a first dielectric layer;
a second interconnect layer over the first interconnect layer, comprising:
a first self-aligned etching stop layer;
a second dielectric layer over the first self-aligned etching stop layer;
a first metal line through the second dielectric layer and the first self-aligned etching stop layer and landing on the first via; and
an encapsulating layer extending between the first self-aligned etching stop layer and the second dielectric layer and between the first metal line and the second dielectric layer,
wherein the first via includes a metal capping layer in direct contact with the first metal line, and a sidewall of the metal capping layer is aligned with a sidewall of the first metal line; and
a third interconnect layer over the second interconnect layer, comprising:
a second self-aligned etching stop layer along an upper surface of the second dielectric layer;
a conformal etching stop layer along an upper surface and a sidewall of the second self-aligned etching stop layer;
a third dielectric layer over the conformal etching stop layer; and
a second via through the third dielectric layer, the conformal etching stop layer and the second self-aligned etching stop layer and landing on the first metal line,
wherein the second self-aligned etching stop layer extends beyond an end of the conformal etching stop layer, and the second via further lands on a portion of the second self-aligned etching stop layer extending beyond the conformal etching stop layer.

### Claim 16 (depends on 15)

The interconnect structure as claimed in claim 15, wherein:
the second interconnect layer further comprises a second metal line separated from the first metal line by the second dielectric layer, and
the conformal etching stop layer covers the second metal line while the second self-aligned etching stop layer does not cover the second metal line.

### Claim 17 (depends on 15)

The interconnect structure as claimed in claim 15, further comprising:
a blocking layer between the first via and the metal line.

### Claim 18 (depends on 10)

The interconnect structure as claimed in claim 10, wherein a top surface of the first portion of the encapsulating layer and a top surface of the second portion of the encapsulating layer are covered by and in direct contact with the second portion of the first etching stop layer.

### Claim 19 (depends on 10)

The interconnect structure as claimed in claim 10, further comprising:
a second via below the first metal line, wherein the second via includes a metal bulk layer and a metal capping layer over the metal bulk layer and in direct contact with the first metal line.

### Claim 20 (depends on 19)

The interconnect structure as claimed in claim 19, wherein a sidewall of the metal capping layer is aligned with a sidewall of the second etching stop layer.