# US 12,009,296 B2 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,296 B2 - Document ID: US12009296B2 - Status: Granted - Kind: B2 - Application number: 17/461,924 - Filed: 2021-08-30 - Published: 2023-03-02 - Granted: 2024-06-11 - Earliest claimed: 2021-08-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Wei-Kai Shih - Web page: https://patentgrep.com/patent/US12009296B2 ## CPC - H10W 20/43: Layouts of interconnections - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/019: {of bond pads} - H10W 72/90: Bond pads, in general - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/29: Bond pads specially adapted therefor - H10W 74/147: {the encapsulations being multilayered} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor device and method of forming the same are disclosed. One of the semiconductor devices includes a semiconductor substrate, a passivation layer and a conductive pattern. The semiconductor substrate includes a conductive pad thereover. The passivation layer over the semiconductor substrate. The conductive pattern is penetrating through the passivation layer and electrically connected to the conductive pad, wherein a sidewall of the conductive pattern has at least one turning point. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate, comprising a conductive pad thereover; a passivation layer over the semiconductor substrate; a post-passivation interconnect (PPI) structure, disposed over the passivation layer and electrically connected to the conductive pad, wherein the PPI structure comprises a first portion including a first sidewall, a second sidewall and a bottom, the second sidewall is disposed between the first sidewall and the bottom, a first angle formed between the first sidewall and the second sidewall is an obtuse angle, and a second angle formed between the second sidewall and the bottom is an obtuse angle, wherein part of the first portion is partially embedded in the conductive pad; and a conductive terminal, disposed over and electrically connected to the PPI structure. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the first sidewall is a substantially vertical to the bottom. ### Claim 3 (depends on 1) The semiconductor device as claimed in claim 1, wherein the semiconductor substrate comprises an active device, and an interconnect structure between the active device and the conductive pad. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein the PPI structure comprises a second portion, and the second portion of the PPI structure extends over the passivation layer and electrically connected to the first portion and the conductive terminal. ### Claim 5 A semiconductor device, comprising: a semiconductor substrate, comprising a conductive pad thereover; a passivation layer over the semiconductor substrate; a post-passivation interconnect (PPI) structure disposed over the passivation layer and electrically connected to the conductive pad, wherein the PPI structure comprises a first portion including a first sidewall, a second sidewall and a bottom, the second sidewall being disposed between the first sidewall and the bottom, wherein a first angle formed between the first sidewall and the second sidewall is an obtuse angle, and a second angle formed between the second sidewall and the bottom is an obtuse angle, wherein the conductive pad has an inclined sidewall contacting with and electrically connecting to the first portion of the PPI structure; and a conductive terminal, disposed over and electrically connected to the PPI structure. ### Claim 6 (depends on 5) The semiconductor device as claimed in claim 5, wherein the conductive pattern penetrates the passivation layer to electrically connect the conductive pad. ### Claim 7 (depends on 5) The semiconductor device as claimed in claim 5, wherein the first angle is substantially formed at a same level with an interface of the passivation layer and the conductive pad. ### Claim 8 (depends on 5) The semiconductor device as claimed in claim 5, wherein the first angle is formed at a lower level with respect to an interface of the passivation layer and the conductive pad. ### Claim 9 (depends on 5) The semiconductor device as claimed in claim 5, wherein the first sidewall is in direct contact with the passivation layer. ### Claim 10 (depends on 5) The semiconductor device as claimed in claim 5, wherein the first sidewall is in direct contact with the passivation layer and the conductive pad. ### Claim 11 (depends on 5) The semiconductor device as claimed in claim 5, wherein the first portion further includes a horizontal sidewall connecting the first sidewall, and the first sidewall is disposed between the horizontal sidewall and the second sidewall. ### Claim 12 (depends on 5) The semiconductor device as claimed in claim 5, wherein a topmost surface of the first portion has a recess above the bottom, and a sidewall and a bottom of the recess is substantially conformal with the second sidewall and the bottom of the first portion. ### Claim 13 (depends on 5) The semiconductor device as claimed in claim 5, wherein the first portion further comprises a third sidewall, the first sidewall is disposed between the second and third sidewalls, and a third angle formed between the third sidewall and the second sidewall is an obtuse angle. ### Claim 14 (depends on 5) The semiconductor device as claimed in claim 5, wherein the conductive pad further comprises a horizontal portion and a bottom, the inclined sidewall is disposed between the horizontal portion and the bottom, and the horizontal portion is in direct contact with the passivation layer. ### Claim 15 A semiconductor device, comprising: a semiconductor substrate, comprising a conductive pad thereover; a passivation layer over the semiconductor substrate; a post-passivation interconnect (PPI) structure, disposed over the passivation layer and electrically connected to the conductive pad, wherein the PPI structure comprises a first portion including a first surface, a first sidewall, a second sidewall and a bottom, the first surface is in direct contact with the passivation layer, the first sidewall is disposed between the first surface and the second sidewall, the second sidewall is disposed between the first sidewall and the bottom, a first angle formed between the first sidewall and the second sidewall is an obtuse angle, and a second angle formed between the second sidewall and the bottom is an obtuse angle; and a conductive terminal, disposed over and electrically connected to the PPI structure. ### Claim 16 (depends on 15) The semiconductor device as claimed in claim 15, wherein a projection of the first portion of the PPI structure onto the semiconductor substrate is not overlapped with a projection of the conductive terminal onto the semiconductor substrate. ### Claim 17 (depends on 15) The semiconductor device as claimed in claim 15, further comprising an under bump metallization (UBM) layer disposed between and in direct contact with the conductive terminal and the PPI structure. ### Claim 18 (depends on 17) The semiconductor device as claimed in claim 17, wherein a projection of the first portion of the PPI structure onto the semiconductor substrate is not overlapped with a projection of the UBM layer onto the semiconductor substrate. ### Claim 19 (depends on 15) The semiconductor device as claimed in claim 15, wherein the first surface is substantially parallel to the bottom. ### Claim 20 (depends on 15) The semiconductor device as claimed in claim 15, wherein the first surface is extended on the passivation layer.