# US 12,009,295 B2 · Comb / fishbone metal stack

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- Number: US 12,009,295 B2
- Document ID: US12009295B2
- Status: Granted
- Kind: B2
- Application number: 17/454,203
- Filed: 2021-11-09
- Published: 2023-05-11
- Granted: 2024-06-11
- Earliest claimed: 2021-11-09
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Thomas Hua-Min Williams; Matthew Chauncey Kusbit; Luis Chen; Keyurkumar Karsanbhai Kansagra; Smeeta Heggond
- Web page: https://patentgrep.com/patent/US12009295B2

## CPC

- H10D 89/10: Integrated device layouts
- H10W 20/43: Layouts of interconnections
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10D 84/907: {CMOS gate arrays}
- H10D 84/975: {Wiring regions or routing}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

## Claims

### Claim 1

An integrated circuit (IC), comprising:
a first set of metal oxide semiconductor (MOS) transistors, the first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B;
a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A, each interconnect stack of the first plurality of interconnect stacks extending in a second direction over at least a portion of the first set of MOS transistors and including consecutive metal layer interconnects; and
a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks, the first comb interconnect structure being coupled to the first plurality of interconnect stacks, wherein
each interconnect stack of the first plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the first plurality of interconnect stacks, wherein i=1 and q>=4, and the first comb interconnect structure is on a metal q (Mq) layer.

### Claim 2 (depends on 1)

The IC of claim 1, further comprising a second plurality of interconnect stacks extending in the second direction over at least a portion of the first set of MOS transistors, the second plurality of interconnect stacks being coupled to the first transistor source/drain terminal B, each interconnect stack of the second plurality of interconnect stacks including consecutive metal layer interconnects.

### Claim 3 (depends on 2)

The IC of claim 2, wherein:
each interconnect stack of the second plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the second plurality of interconnect stacks.

### Claim 4 (depends on 2)

The IC of claim 2, wherein a pair of interconnect stacks of the second plurality of interconnect stacks is between each adjacent pair of interconnect stacks of the first plurality of interconnect stacks.

### Claim 5 (depends on 2)

The IC of claim 2, wherein a pair of interconnect stacks of the first plurality of interconnect stacks is between each adjacent pair of interconnect stacks of the second plurality of interconnect stacks.

### Claim 6 (depends on 2)

The IC of claim 2, further comprising a second comb interconnect structure extending in the first direction, with comb fingers extending in the second direction over at least a portion of the second plurality of interconnect stacks, the second comb interconnect structure being coupled to the second plurality of interconnect stacks, the first comb interconnect structure and the second comb interconnect structure being on a same metal layer.

### Claim 7 (depends on 6)

The IC of claim 6, wherein the second comb interconnect structure has a density of the comb fingers double a density of the comb fingers of the first comb interconnect structure.

### Claim 8 (depends on 6)

The IC of claim 6, wherein the first comb interconnect structure has a density of the comb fingers double a density of the comb fingers of the second comb interconnect structure.

### Claim 9 (depends on 6)

The IC of claim 6, further comprising a third plurality of interconnect stacks extending in the second direction over at least a portion of the first set of MOS transistors, the third plurality of interconnect stacks being coupled to the first transistor gate, each interconnect stack of the third plurality of interconnect stacks including consecutive metal layer interconnects.

### Claim 10 (depends on 9)

The IC of claim 9, wherein:
each interconnect stack of the third plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the third plurality of interconnect stacks.

### Claim 11 (depends on 9)

The IC of claim 9, wherein each interconnect stack of the third plurality of interconnect stacks is between a corresponding adjacent pair of interconnect stacks of the second plurality of interconnect stacks.

### Claim 12 (depends on 9)

The IC of claim 9, wherein each interconnect stack of the third plurality of interconnect stacks is between a corresponding adjacent pair of interconnect stacks of the first plurality of interconnect stacks.

### Claim 13 (depends on 9)

The IC of claim 9, further comprising a first plurality of interconnects extending in the second direction over at least a portion of the third plurality of interconnect stacks, the first plurality of interconnects being coupled to the third plurality of interconnect stacks, the first plurality of interconnects being on a same metal layer as the first comb interconnect structure and the second comb interconnect structure.

### Claim 14 (depends on 13)

The IC of claim 13, wherein each interconnect of the first plurality of interconnects is between an adjacent pair of the comb fingers of the second comb interconnect structure.

### Claim 15 (depends on 13)

The IC of claim 13, wherein each interconnect of the first plurality of interconnects is between an adjacent pair of the comb fingers of the first comb interconnect structure.

### Claim 16 (depends on 1)

The IC of claim 1, further comprising:
a second set of MOS transistors, the second set of MOS transistors configured to have a common second transistor source/drain terminal B, a second transistor gate, and a second transistor source/drain terminal A; and
a second comb interconnect structure extending in the first direction, with comb fingers extending in the second direction over at least a portion of the second set of MOS transistors and the first plurality of interconnect stacks, the second comb interconnect structure being coupled to the first plurality of interconnect stacks, the first comb interconnect structure and the second comb interconnect structure being configured into a fishbone interconnect structure;
wherein the first plurality of interconnect stacks is coupled to the second transistor source/drain terminal A, and each interconnect stack of the first plurality of interconnect stacks extends in the second direction over at least a portion of the second set of MOS transistors.

### Claim 17 (depends on 16)

The IC of claim 16, further comprising:
a second plurality of interconnect stacks extending in the second direction over at least a portion of the first set of MOS transistors, the second plurality of interconnect stacks being coupled to the first transistor source/drain terminal B, each interconnect stack of the second plurality of interconnect stacks including consecutive metal layer interconnects; and
a third plurality of interconnect stacks extending in the second direction over at least a portion of the second set of MOS transistors, the third plurality of interconnect stacks being coupled to the second transistor source/drain terminal B, each interconnect stack of the third plurality of interconnect stacks including consecutive metal layer interconnects.

### Claim 18 (depends on 17)

The IC of claim 17, wherein:
each interconnect stack of the second plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the second plurality of interconnect stacks;
each interconnect stack of the third plurality of interconnect stacks includes Mp layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the third plurality of interconnect stacks; and
the fishbone interconnect structure is on a metal q (Mq) layer.

### Claim 19 (depends on 17)

The IC of claim 17, wherein:
a pair of interconnect stacks of the second plurality of interconnect stacks is between each adjacent pair of interconnect stacks of the first plurality of interconnect stacks; and
a pair of interconnect stacks of the third plurality of interconnect stacks is between each adjacent pair of interconnect stacks of the first plurality of interconnect stacks.

### Claim 20 (depends on 17)

The IC of claim 17, wherein:
a pair of interconnect stacks of the first plurality of interconnect stacks is between each adjacent pair of interconnect stacks of the second plurality of interconnect stacks; and
a pair of interconnect stacks of the first plurality of interconnect stacks is between each adjacent pair of interconnect stacks of the third plurality of interconnect stacks.

### Claim 21 (depends on 17)

The IC of claim 17, wherein the second plurality of interconnect stacks and the third plurality of interconnect stacks are collinear in the second direction.

### Claim 22 (depends on 17)

The IC of claim 17, further comprising:
a third comb interconnect structure extending in the first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the second plurality of interconnect stacks, the third comb interconnect structure being coupled to the second plurality of interconnect stacks, the third comb interconnect structure and the fishbone interconnect structure being on a same metal layer; and
a fourth comb interconnect structure extending in the first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the third plurality of interconnect stacks, the fourth comb interconnect structure being coupled to the third plurality of interconnect stacks, the fourth comb interconnect structure being on a same metal layer as the fishbone interconnect structure.

### Claim 23 (depends on 22)

The IC of claim 22, wherein the comb fingers of the third comb interconnect structure are collinear in the second direction with the comb fingers of the fourth comb interconnect structure.

### Claim 24 (depends on 22)

The IC of claim 22, wherein the third comb interconnect structure is configured to be coupled to a first voltage source, and the fourth comb interconnect structure is configured to be coupled to a second voltage source different than the first voltage source.

### Claim 25 (depends on 22)

The IC of claim 22, wherein:
the third comb interconnect structure has a density of the comb fingers double a density of the comb fingers of the first comb interconnect structure; and
the fourth comb interconnect structure has a density of the comb fingers double a density of the comb fingers of the second comb interconnect structure.

### Claim 26 (depends on 22)

The IC of claim 22, wherein:
the first comb interconnect structure has a density of the comb fingers double a density of the comb fingers of the third comb interconnect structure; and
the second comb interconnect structure has a density of the comb fingers double a density of the comb fingers of the fourth comb interconnect structure.

### Claim 27 (depends on 22)

The IC of claim 22, further comprising:
a fourth plurality of interconnect stacks extending in the second direction over at least a portion of the first set of MOS transistors, the fourth plurality of interconnect stacks being coupled to the first transistor gate, each interconnect stack of the fourth plurality of interconnect stacks including consecutive metal layer interconnects; and
a fifth plurality of interconnect stacks extending in the second direction over at least a portion of the second set of MOS transistors, the fifth plurality of interconnect stacks being coupled to the second transistor gate, each interconnect stack of the fifth plurality of interconnect stacks including consecutive metal layer interconnects.

### Claim 28 (depends on 27)

The IC of claim 27, wherein:
each interconnect stack of the fourth plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the fourth plurality of interconnect stacks;
each interconnect stack of the fifth plurality of interconnect stacks includes metal p (Mp) layer interconnects for p=i, i+1, . . . , q−1 and corresponding vias Vp for p=i, i+1, . . . , q−2 coupling together each interconnect stack of the fifth plurality of interconnect stacks; and
the fishbone interconnect structure is on a metal q (Mq) layer.

### Claim 29 (depends on 27)

The IC of claim 27, wherein:
each interconnect stack of the fourth plurality of interconnect stacks is between a corresponding adjacent pair of interconnect stacks of the second plurality of interconnect stacks; and
each interconnect stack of the fifth plurality of interconnect stacks is between a corresponding adjacent pair of interconnect stacks of the third plurality of interconnect stacks.

### Claim 30 (depends on 27)

The IC of claim 27, wherein:
each interconnect stack of the fourth plurality of interconnect stacks is between a corresponding adjacent pair of interconnect stacks of the first plurality of interconnect stacks; and
each interconnect stack of the fifth plurality of interconnect stacks is between a corresponding adjacent pair of interconnect stacks of the first plurality of interconnect stacks.

### Claim 31 (depends on 27)

The IC of claim 27, wherein the fourth plurality of interconnect stacks and the fifth plurality of interconnect stacks are collinear in the second direction.

### Claim 32 (depends on 27)

The IC of claim 27, further comprising:
a first plurality of interconnects extending in the second direction over at least a portion of the fourth plurality of interconnect stacks, the first plurality of interconnects being coupled to the fourth plurality of interconnect stacks, the first plurality of interconnects being on a same metal layer as the fishbone interconnect structure; and
a second plurality of interconnects extending in the second direction over at least a portion of the fifth plurality of interconnect stacks, the second plurality of interconnects being coupled to the fifth plurality of interconnect stacks, the second plurality of interconnects being on a same metal layer as the fishbone interconnect structure.

### Claim 33 (depends on 32)

The IC of claim 32, wherein:
each interconnect of the first plurality of interconnects is between a pair of fingers of the third comb interconnect structure; and
each interconnect of the second plurality of interconnects is between a pair of fingers of the fourth comb interconnect structure.

### Claim 34 (depends on 32)

The IC of claim 32, wherein:
each interconnect of the first plurality of interconnects is between a pair of fingers of the first comb interconnect structure; and
each interconnect of the second plurality of interconnects is between a pair of fingers of the second comb interconnect structure.

### Claim 35 (depends on 32)

The IC of claim 32, wherein the first plurality of interconnects and the second plurality of interconnects are collinear in the second direction.

### Claim 36 (depends on 16)

The IC of claim 16, wherein the first set of MOS transistors comprises p-type MOS (pMOS) transistors and the second set of MOS transistors comprises n-type MOS (nMOS) transistors, or the first set of MOS transistors comprises nMOS transistors and the second set of MOS transistors comprises pMOS transistors.

### Claim 37 (depends on 16)

The IC of claim 16, wherein the first set of MOS transistors comprises p-type MOS (pMOS) transistors and the second set of MOS transistors comprises pMOS transistors.

### Claim 38 (depends on 16)

The IC of claim 16, wherein the first set of MOS transistors comprises n-type MOS (nMOS) transistors and the second set of MOS transistors comprises nMOS transistors.

### Claim 39 (depends on 16)

The IC of claim 16, wherein the first transistor source/drain terminal A and the second transistor source/drain terminal A are configured as drains, and the first transistor source/drain terminal B and the second transistor source/drain terminal B are configured as sources.

### Claim 40 (depends on 16)

The IC of claim 16, wherein the first transistor source/drain terminal A and the second transistor source/drain terminal A are configured as sources, and the first transistor source/drain terminal B and the second transistor source/drain terminal B are configured as drains.

### Claim 41 (depends on 1)

The IC of claim 1, wherein the first set of MOS transistors comprises p-type MOS (pMOS) transistors or n-type MOS (nMOS) transistors.

### Claim 42 (depends on 1)

The IC of claim 1, wherein the consecutive metal layer interconnects in each interconnect stack of the first plurality of interconnect stacks are unidirectional in the second direction.

### Claim 43 (depends on 1)

The IC of claim 1, wherein q=5.

### Claim 44 (depends on 1)

The IC of claim 1, further comprising:
a set of middle-end-of-line (MEOL) interconnects coupled to the first transistor source/drain terminal A, the set of MEOL interconnects being on one or more layers lower than the first plurality of interconnect stacks; and
a set of back-end-of-line (BEOL) interconnects coupled to the set of MEOL interconnects, the set of BEOL interconnects being on one or more layers lower than the first plurality of interconnect stacks, the first plurality of interconnect stacks being coupled to the set of BEOL interconnects.

### Claim 45 (depends on 1)

The IC of claim 1, wherein the first transistor source/drain terminal A is configured as a drain, and the first transistor source/drain terminal B is configured as a source.

### Claim 46 (depends on 1)

The IC of claim 1, wherein the first transistor source/drain terminal A is configured as a source, and the first transistor source/drain terminal B is configured as a drain.