# US 12,009,294 B2 · Middle-of-line interconnect structure and manufacturing method

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- Number: US 12,009,294 B2
- Document ID: US12009294B2
- Status: Granted
- Kind: B2
- Application number: 17/875,533
- Filed: 2022-07-28
- Published: 2022-11-17
- Granted: 2024-06-11
- Earliest claimed: 2019-09-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Wei Chang; Sung-Li Wang; Yi-Ying Liu; Chia-Hung Chu; Fang-Wei Lee
- Web page: https://patentgrep.com/patent/US12009294B2

## CPC

- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10W 20/42: Vias, e.g. via plugs
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 14/418: {the conductive layers comprising transition metals}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/0526: {by thermal treatment thereof}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

## Claims

### Claim 1

A method of manufacturing an integrated circuit device, comprising:
forming a lower inter-layer dielectric (ILD) layer over a substrate;
forming a lower conductive plug through the lower ILD layer on a source/drain region of a transistor structure;
forming a capping layer on the lower conductive plug;
forming an upper ILD layer over the lower ILD layer and the capping layer; and
forming an upper conductive plug through the upper ILD layer reaching the capping layer;
wherein the upper conductive plug is formed by forming a metal core followed by an annealing process to form an intermixing barrier layer lining an interface of the metal core and the upper ILD layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the upper conductive plug further comprises:
performing a first etching process to form a first opening extending through the upper ILD layer and below a top surface of the lower ILD layer,
performing a second etching process to form a second opening overlapping the first opening and extending to a top surface of the capping layer, and
filling the first opening and the second opening with a conductive material, forming the metal core.

### Claim 3 (depends on 1)

The method of claim 1, wherein a bottom surface of the capping layer is below an upper surface of the lower ILD layer and above a bottom surface of the metal core.

### Claim 4 (depends on 1)

The method of claim 1, wherein the intermixing barrier layer does not extend beneath an upper surface of the lower ILD layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a lower barrier layer surrounding sidewalls of the lower conductive plug, wherein the lower barrier layer contacts a bottom surface of the metal core.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a gate electrode between the source/drain region and a second source/drain region before the forming of the lower conductive plug, wherein after the forming of the upper conductive plug, the upper conductive plug contacts the gate electrode.

### Claim 7 (depends on 6)

The method of claim 6, wherein the metal core of the upper conductive plug contacts a barrier layer of the gate electrode.

### Claim 8

A method of manufacturing an integrated circuit device, comprising:
forming a lower inter-layer dielectric (ILD) layer over a substrate;
forming an etch stop layer over the lower ILD layer;
forming a lower conductive plug through the lower ILD layer and the etch stop layer over a source/drain region of a transistor structure;
forming an upper ILD layer over the lower ILD layer and the etch stop layer; and
forming an upper conductive plug through the upper ILD layer and extending into the etch stop layer;
wherein the upper conductive plug is formed by forming a metal core followed by an annealing process to form an intermixing barrier layer lining an interface of the metal core and the upper ILD layer, a bottommost surface of the intermixing barrier layer overlying the etch stop layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the etch stop layer extends beneath an upper surface of the lower ILD layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the upper conductive plug extends to a bottom surface of the etch stop layer.

### Claim 11 (depends on 8)

The method of claim 8, wherein the etch stop layer extends between a first lower surface of the upper conductive plug and a second lower surface of the upper conductive plug.

### Claim 12 (depends on 8)

The method of claim 8, further comprising forming a lower barrier layer before forming the lower conductive plug, wherein the lower conductive plug is spaced from the etch stop layer by the lower barrier layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the lower barrier layer extends from the source/drain region to a lower surface of the metal core.

### Claim 14 (depends on 12)

The method of claim 12, further comprising forming a capping layer after forming the lower conductive plug, wherein the lower barrier layer covers whole surfaces of the capping layer and lower conductive plug.

### Claim 15

A method of manufacturing an integrated circuit device, comprising:
forming a lower inter-layer dielectric (ILD) layer over a substrate;
forming an etch stop layer over the lower ILD layer;
forming a lower barrier layer, the lower barrier layer surrounding inner sidewalls of the lower ILD layer and extending to a top surface of the etch stop layer;
forming a lower conductive plug through the lower ILD layer and the etch stop layer reaching a source/drain region of a transistor structure, the lower conductive plug having a top surface below a top surface of the lower barrier layer;
forming a capping layer on the lower conductive plug; and
forming an upper conductive plug over the capping layer, the upper conductive plug extending beneath the capping layer and contacting a top surface and a bottom surface of the etch stop layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the capping layer has a top surface that is substantially coplanar with a top surface of the etch stop layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the etch stop layer extends from an elevation level with a top surface of the capping layer to an elevation level with a bottom surface of the upper conductive plug.

### Claim 18 (depends on 15)

The method of claim 15, wherein the capping layer has a top surface that is substantially coplanar with a top surface of the lower barrier layer.

### Claim 19 (depends on 15)

The method of claim 15, wherein inner sidewalls of the lower barrier layer surround outer sidewalls of the capping layer, and outer sidewalls of the lower barrier layer are surrounded by the etch stop layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the upper conductive plug further comprises:
performing a first etching process to form a first opening extending through the etch stop layer to a bottom surface of the etch stop layer;
performing a second etching process to form a second opening overlapping the first opening and extending to a top surface of the capping layer;
filling the first opening and the second opening with a conductive material, forming a metal core of the upper conductive plug; and
performing an annealing process, forming an intermixing barrier layer along sidewalls of the upper conductive plug above the etch stop layer.