# US 12,009,292 B2 · Metal-insulator-metal (MIM) capacitor structure for layer count reduction and lower capacitance variation

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- Number: US 12,009,292 B2
- Document ID: US12009292B2
- Status: Granted
- Kind: B2
- Application number: 17/547,093
- Filed: 2021-12-09
- Published: 2023-06-15
- Granted: 2024-06-11
- Earliest claimed: 2021-12-09
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Nosun Park; Changhan Hobie Yun; Daniel Daeik Kim; Paragkumar Ajaybhai Thadesar; Sameer Sunil Vadhavkar
- Web page: https://patentgrep.com/patent/US12009292B2

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 1/20: Inductors
- H10D 1/68: Capacitors having no potential barriers
- H10D 1/714: {having horizontal extensions}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit (IC) includes a substrate and a first metal-insulator-metal (MIM) capacitor. The first MIM capacitor includes a first plate comprising a first metallization layer on a surface of the substrate. The first MIM capacitor also includes a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate. The first MIM capacitor further includes a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer. The IC also includes an inductor comprising a portion of the second plate on the second portion of the surface of the substrate.

## Claims

### Claim 1

An integrated circuit (IC), comprising:
a substrate;
a first metal-insulator-metal (MIM) capacitor comprising:
a first plate comprising a first metallization layer on a surface of the substrate,
a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate, and
a second plate on the first MIM insulator layer and on a second portion of the surface of the substrate, the second plate comprising a second metallization layer;
an inductor comprising a portion of the second plate on the second portion of the surface of the substrate; and
a second MIM capacitor, which comprises:
the first plate on the surface of the substrate,
a second MIM insulator layer on a second portion of the surface of the first plate; and
a third plate on the second MIM insulator layer.

### Claim 2 (depends on 1)

The IC of claim 1, further comprising a first via coupled to the portion of the second plate on the second portion of the surface of the substrate.

### Claim 3 (depends on 2)

The IC of claim 2, in which the inductor further comprises the first via and a third metallization layer on the first via.

### Claim 4 (depends on 1)

The IC of claim 1, in which the second plate is on a sidewall of the first MIM insulator layer and on the first MIM insulator layer on the first portion of the surface of the substrate.

### Claim 5 (depends on 1)

The IC of claim 1, in which an X-axis width of the second plate is greater than an X-axis width of the first plate.

### Claim 6 (depends on 1)

The IC of claim 1, in which an X-axis width of the first MIM insulator layer is greater than an X-axis width of the first plate.

### Claim 7 (depends on 1)

The IC of claim 1, in which the IC is integrated in an integrated passive device (IPD).

### Claim 8 (depends on 7)

The IC of claim 7, in which the IPD is integrated in a radio frequency (RF) filter.

### Claim 9 (depends on 7)

The IC of claim 7, in which the IPD is integrated in a radio frequency (RF) module.

### Claim 10

A method for fabricating an integrated circuit (IC), comprising:
depositing a first metallization layer on a surface of a substrate as a first plate of a first metal-insulator-metal (MIM) capacitor;
depositing a first MIM insulator layer on a first portion of a surface of the first plate, a sidewall of the first plate, and a first portion of the surface of the substrate;
depositing a second metallization layer on the first MIM insulator layer and on a second portion of the surface of the substrate as a second plate of the first MIM capacitor;
forming an inductor comprising a portion of the second plate on the second portion of the surface of the substrate;
forming a second MIM insulator layer on a second portion of the surface of the first plate; and
forming a third plate on the second MIM insulator layer.

### Claim 11 (depends on 10)

The method of claim 10, in which forming the inductor comprises:
forming a first via coupled to the portion of the second plate on the second portion of the surface of the substrate; and
depositing a third metallization layer on the first via.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
depositing a first passivation layer on the first MIM capacitor; and
depositing a second passivation layer on the inductor and the first passivation layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
exposing a surface of the inductor through the second passivation layer;
forming an under bump metallization (UBM) layer on the surface of the inductor and on sidewalls and a portion of a surface of the second passivation layer; and
forming a bump interconnect on the UBM layer.

### Claim 14 (depends on 10)

The method of claim 10, in which depositing the second metallization layer comprises depositing the second metallization layer on a sidewall of the first MIM insulator layer and on the first MIM insulator layer on the first portion of the surface of the substrate.

### Claim 15 (depends on 10)

The method of claim 10, further comprising integrating the IC in an integrated passive device (IPD).

### Claim 16 (depends on 15)

Method of claim 15, further comprising integrating the IPD in a radio frequency (RF) filter.

### Claim 17 (depends on 15)

The method of claim 15, further comprising integrating the IPD in a radio frequency (RF) module.

### Claim 18 (depends on 10)

The method of claim 10, in which the substrate comprises glass.