# US 12,009,289 B2 · Semiconductor package and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,289 B2 - Document ID: US12009289B2 - Status: Granted - Kind: B2 - Application number: 17/501,857 - Filed: 2021-10-14 - Published: 2022-02-17 - Granted: 2024-06-11 - Earliest claimed: 2015-07-13 - Assignees: Amkor Technology Singapore Holding Pte. Ltd. - Applicants: Amkor Technology Singapore Holding Pte Ltd. - Inventors: Jae Ung Lee; Yung Woo Lee; EunNaRa Cho; Dong Hyun Bang; Wook Choi; KooWoong Jeong; Byong Jin Kim; Min Chul Shin; Ho Jeong Lim; Ji Hyun Kim; Chang Hun Kim - Web page: https://patentgrep.com/patent/US12009289B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/095: {of vias therein} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H10W 72/00: Interconnections or connectors in packages - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns. ## Claims ### Claim 1 A semiconductor package comprising: a substrate comprising: a first substrate surface; a second substrate surface opposite the first substrate surface; a recess portion in the first substrate surface and extending toward the second substrate surface; a plurality of recess conductive patterns in the recess portion; a dielectric layer having a first dielectric surface, a second dielectric surface, and a side dielectric surface extending between the first dielectric surface and the second dielectric surface, wherein the recess portion extends from the first dielectric surface to the second dielectric surface adjacent the side dielectric surface; a first conductive pattern at the first dielectric surface; a second conductive pattern at the second dielectric surface; and a conductive via that passes through the dielectric layer and electrically connects the first conductive pattern and the second conductive pattern; a passive element positioned in the recess portion of the substrate and comprising a first electrode and a second electrode, each electrically connected to a respective pattern of the plurality of recess conductive patterns; a semiconductor die mounted on the first dielectric surface and connected to the first conductive pattern; a layer of a single continuous encapsulating material that contacts the side dielectric surface, covers at least a first side and lateral sides of the passive element, covers at least a portion of the first substrate surface, and covers at least lateral sides of the semiconductor die and a first side of the semiconductor die facing away from the dielectric layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein: the first side of the passive element faces away from the substrate, and the first side of the passive element is lower than the first side of the semiconductor die; and no portion of the semiconductor die covers the recess portion or any other recess portion of the substrate. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein no portion of the passive element is covered by an electronic component coupled to the first substrate surface. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the second conductive pattern extends outward from the second dielectric surface. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the encapsulating material underfills the passive element. ### Claim 6 (depends on 1) The semiconductor package of claim 1, comprising a conductive bump electrically coupled to the second conductive pattern. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the dielectric layer comprises an organic dielectric material. ### Claim 8 (depends on 1) The semiconductor package of claim 1, comprising a volume that laterally surrounds the passive element, the volume filled by the layer of the single continuous encapsulating material. ### Claim 9 A semiconductor package comprising: a substrate comprising: a first substrate side; a second substrate side opposite the first substrate side; a recess portion in the first substrate side and extending toward the second substrate side; a plurality of recess conductive patterns in the recess portion; a dielectric layer having a first dielectric surface, a second dielectric surface, and side dielectric surfaces extending between the first dielectric surface and the second dielectric surface, wherein the recess portion extends from the first dielectric surface to the second dielectric surface between the side dielectric surfaces; a first conductive pattern at the first dielectric surface; a second conductive pattern at the second dielectric surface; and a conductive via that passes through the dielectric layer and electrically connects the first conductive pattern and the second conductive pattern; a passive element positioned in the recess portion of the substrate and comprising a first electrode and a second electrode, each electrically connected to a respective pattern of the plurality of recess conductive patterns; a semiconductor die mounted on the first dielectric surface and connected to the first conductive pattern; a layer of a single continuous encapsulating material that covers at least a first side and lateral sides of the passive element, and covers at least lateral sides of the semiconductor die and a first side of the semiconductor die facing away from the dielectric layer. ### Claim 10 A method of manufacturing a semiconductor package, the method comprising: providing a substrate comprising: a first substrate surface; a second substrate surface opposite the first substrate surface; a recess portion in the first substrate surface and extending toward the second substrate surface; a plurality of recess conductive patterns in the recess portion; a dielectric layer having a first dielectric surface and a second dielectric surface, wherein the recess portion extends from the first dielectric surface to the second dielectric surface; a first conductive pattern at the first dielectric surface; a second conductive pattern at the second dielectric surface; and a conductive via that passes through the dielectric layer and electrically connects the first conductive pattern and the second conductive pattern; positioning a passive element in the recess portion of the substrate and electrically connecting a first electrode and a second electrode of the passive element to a respective pattern of the plurality of recess conductive patterns; mounting a semiconductor die on the first dielectric surface and connecting the semiconductor die to the first conductive pattern; and providing a layer of a single continuous encapsulating material that covers at least a first side and lateral sides of the passive element, and covers at least lateral sides of the semiconductor die and a first side of the semiconductor die facing away from the dielectric layer. ### Claim 11 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein the substrate comprises a seed layer between the conductive via and the first conductive pattern and on a side surface of the conductive via. ### Claim 12 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein the first dielectric surface and a surface of the first conductive pattern are coplanar. ### Claim 13 (depends on 12) The method of manufacturing the semiconductor package of claim 12, wherein the second conductive pattern extends outward from the second dielectric surface. ### Claim 14 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein the first side of the passive element faces away from the substrate, and the first side of the passive element is lower than the first side of the semiconductor die. ### Claim 15 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein the encapsulating material underfills the passive element. ### Claim 16 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein no portion of the semiconductor die covers the recess portion or any other recess portion of the substrate. ### Claim 17 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein a top surface of the first conductive pattern is coplanar with the first dielectric layer surface. ### Claim 18 (depends on 10) The method of manufacturing the semiconductor package of claim 10, comprising providing a conductive bump electrically coupled to the second conductive pattern, wherein at least a portion of the conductive bump is exposed to an outside of the semiconductor package. ### Claim 19 (depends on 10) The method of manufacturing the semiconductor package of claim 10, wherein a first end of the conductive via at the first conductive pattern is narrower than a second end of the conductive via at the second conductive pattern. ### Claim 20 (depends on 10) The method of manufacturing the semiconductor package of claim 10, comprising a seed layer, wherein the second conductive pattern is separated from the second dielectric surface by at least the seed layer, and the first conductive pattern directly contacts the first dielectric layer surface.