# US 12,009,288 B2 · Interconnection structure and semiconductor package including the same

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- Number: US 12,009,288 B2
- Document ID: US12009288B2
- Status: Granted
- Kind: B2
- Application number: 17/230,511
- Filed: 2021-04-14
- Published: 2022-02-24
- Granted: 2024-06-11
- Earliest claimed: 2020-08-24
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongjoon Oh; Junyun Kweon; Jumyong Park; Jin Ho An; Chungsun Lee; Hyunsu Hwang
- Web page: https://patentgrep.com/patent/US12009288B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

## Claims

### Claim 1

An interconnection structure, comprising:
a first dielectric layer and a first hardmask pattern that are sequentially stacked; and
a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer, wherein
the first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer,
the first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other,
the first pad part vertically overlapping the via part,
the line part extends from the first pad part,
a level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part,
a top surface of the first pad part and a top surface of the line part are coplanar with a top surface of the first hardmask pattern, and
the bottom surface of the first pad part, the bottom surface of the line part, and a lateral surface of the via part are in contact with the first dielectric layer.

### Claim 2 (depends on 1)

The interconnection structure of claim 1, further comprising:
a second hardmask pattern below the first dielectric layer;
a second dielectric layer below the second hardmask pattern; and
a second interconnection pattern that penetrates the second hardmask pattern and the second dielectric layer,
wherein each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer, and
wherein a density of the second hardmask pattern is different from a density of the first hardmask pattern.

### Claim 3 (depends on 1)

The interconnection structure of claim 1, further comprising:
a second hardmask pattern below the first dielectric layer;
a second dielectric layer below the second hardmask pattern; and
a second interconnection pattern that penetrates the second hardmask pattern and the second dielectric layer,
wherein each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer, and
wherein a composition of silicon and oxygen in the second hardmask pattern is different from a composition of silicon and oxygen in the first hardmask pattern.

### Claim 4 (depends on 1)

The interconnection structure of claim 1, wherein a level difference between the bottom surface of the first pad part and the bottom surface of the line part is in a range of 0.3 μm to 0.8 μm.

### Claim 5 (depends on 1)

The interconnection structure of claim 1, wherein a thickness of the first pad part is 1.1 times to 1.25 times a thickness of the line part.

### Claim 6 (depends on 1)

The interconnection structure of claim 1, wherein the first dielectric layer includes at least one of polyimide, polybenzoxazole, phenolic polymers, and benzocyclobutene polymers.

### Claim 7 (depends on 1)

The interconnection structure of claim 1, wherein a sidewall of the via part has a rounded shape.

### Claim 8 (depends on 1)

The interconnection structure of claim 1, wherein a slope of a sidewall of the via part decreases as the sidewall approaches a top region of the via part from a bottom surface of the via part.

### Claim 9 (depends on 1)

The interconnection structure of claim 1, wherein
the first interconnection pattern further includes a second pad part,
the second pad part is integrally connected to a distal end of the line part such that the line part is between the first pad part and the second pad part,
a level of a bottom surface of the second pad part is lower than the level of the bottom surface of the line part, and
a level of the bottom surface of the via part is lower than a level of a bottom surface of the second pad part.

### Claim 10

A semiconductor package, comprising:
a first redistribution substrate;
a first semiconductor apparatus on the first redistribution substrate; and
a first molding member covering the first semiconductor apparatus and the first redistribution substrate, wherein
the first redistribution substrate includes a first dielectric layer, a first hardmask pattern, a second dielectric layer, a second hardmask pattern, a first interconnection pattern, and a second interconnection pattern,
the first dielectric layer, the first hardmask pattern, the second dielectric layer, and the second hardmask pattern that are sequentially stacked,
the first interconnection pattern penetrates the first hardmask pattern and the first dielectric layer, and
the second interconnection pattern penetrates the second hardmask pattern and the second dielectric layer, and
the second interconnection pattern is connected to the first interconnection pattern,
the first hardmask pattern and the second hardmask pattern include a dielectric material having an etch selectivity with respect to the first dielectric layer and the second dielectric layer, respectively,
the second interconnection pattern includes a first via part, a first pad part, and a first line part that are integrally connected to each other,
the first pad part vertically overlaps the first via part,
the first line part extends from the first pad part,
a width of the first pad part is greater than a width of the first line part, and
a level of a bottom surface of the first pad part is lower than a level of a bottom surface of the first line part, and
a top surface of the first pad part is level with a top surface of the first line part.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein
each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer, and
a density of the second hardmask pattern is different from a density of the first hardmask pattern.

### Claim 12 (depends on 10)

The semiconductor package of claim 10, wherein
each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer, and
a composition of silicon and oxygen in the second hardmask pattern is different from a composition of silicon and oxygen in the first hardmask pattern.

### Claim 13 (depends on 10)

The semiconductor package of claim 10, wherein
the top surface of the first pad part and the top surface of the first line part are coplanar with a top surface of the second hardmask pattern,
the bottom surface of the first pad part, the bottom surface of the first line part, and a lateral surface of the first via part are in contact with the second dielectric layer,
the second interconnection pattern further includes a second pad part,
the second pad part is integrally connected to a distal end of the first line part such that the first line part is between the first pad part and the second pad part,
a level of a bottom surface of the second pad part is lower than the level of the bottom surface of the first line part, and
a level of the bottom surface of the first via part is lower than a level of a bottom surface of the second pad part.

### Claim 14 (depends on 10)

The semiconductor package of claim 10, further comprising:
a second redistribution substrate on the first molding member; and
a mold via that penetrates the first molding member and connects the first redistribution substrate to the second redistribution substrate, wherein
the second redistribution substrate includes a third dielectric layer, a third hardmask pattern, and a third interconnection pattern,
the third dielectric layer and the third hardmask pattern that are sequentially stacked,
the third interconnection pattern penetrates the third hardmask pattern and the third dielectric layer,
the third interconnection pattern includes a second via part, a second pad part, and a second line part that are integrally connected to each other,
the second pad part vertically overlaps the second via part,
the second line part extends from the second pad part, and
a level of a bottom surface of the second pad part is lower than a level of a bottom surface of the second line part.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the first hardmask pattern, the second hardmask pattern, and the third hardmask pattern have different densities from each other.

### Claim 16 (depends on 14)

The semiconductor package of claim 14, wherein the first hardmask pattern, the second hardmask pattern, and the third hardmask pattern are different from each other in terms of composition of silicon and oxygen.

### Claim 17

A semiconductor package, comprising:
a first redistribution substrate;
a first semiconductor apparatus on the first redistribution substrate; and
a first molding member covering the first semiconductor apparatus and the first redistribution substrate, wherein
the first redistribution substrate includes a first dielectric layer, a first hardmask pattern, a second dielectric layer, a second hardmask pattern, a first interconnection pattern, and a second interconnection pattern,
the first dielectric layer, the first hardmask pattern, the second dielectric layer, and the second hardmask pattern are sequentially stacked,
the second interconnection pattern is connected to the first interconnection pattern,
the first interconnection pattern penetrates the first hardmask pattern and the first dielectric layer,
the second interconnection pattern penetrates the second hardmask pattern and the second dielectric layer,
each of the first hardmask pattern and the second hardmask pattern includes a silicon oxide layer,
a density of the second hardmask pattern is different from a density of the first hardmask pattern,
the second interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other,
a top surface of the first pad part and a top surface of the line part are coplanar with a top surface of the second hardmask patter,
a bottom surface of the first pad part, a bottom surface of the line part, and a lateral surface of the via part are in contact with the second dielectric layer, and
a bottom surface of the via part is level with a top surface of the first hardmask pattern.

### Claim 18 (depends on 17)

The semiconductor package of claim 17, wherein
the second interconnection pattern further includes a second pad part,
the first pad part vertically overlaps the via part,
the line part extends from the first pad part,
a width of the first pad part is greater than a width of the line part, and
a level of the bottom surface of the first pad part is lower than the level of a bottom surface of the line part,
the second pad part is integrally connected to a distal end of the line part such that the line part is between the first pad part and the second pad part,
a level of a bottom surface of the second pad part is lower than the level of the bottom surface of the line part, and
a level of the bottom surface of the via part is lower than a level of a bottom surface of the second pad part.

### Claim 19 (depends on 17)

The semiconductor package of claim 17, wherein the first hardmask pattern and second hardmask pattern are different from each other in terms of a composition of silicon and oxygen.