# US 12,009,282 B2 · Memory device and memory device module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,282 B2 - Document ID: US12009282B2 - Status: Granted - Kind: B2 - Application number: 18/258,190 - Filed: 2021-03-11 - Published: 2023-12-21 - Granted: 2024-06-11 - Earliest claimed: 2021-03-11 - Assignees: Meiko Electronics Co., Ltd. - Applicants: Meiko Electronics Co., Ltd. - Inventors: Shuzo Akejima - Web page: https://patentgrep.com/patent/US12009282B2 ## CPC - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H10W 40/10: Arrangements for heating - H10W 72/00: Interconnections or connectors in packages - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A memory device includes: a wiring substrate including a multilevel wiring layer and first and second surfaces at opposite sides; a control element embedded in the wiring substrate and having first and second element surfaces at opposite sides, with multiple electrode pads connected to the multilevel wiring layer at the first element surface; a first heat dissipation member at a region of the first surface overlapping the control element; a heat dissipation structure facing the second element surface and exposed at the second surface; and at least one memory element connected with the multilevel wiring layer at a first surface region not overlapping the control element. The multilevel wiring layer includes a signal pattern electrically connecting the control element with the memory element or the external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member. ## Claims ### Claim 1 A memory device, comprising: a wiring substrate including a first surface, a second surface, and a multilevel wiring layer, the second surface being at a side opposite to the first surface; a control element embedded in the wiring substrate, the control element including a first element surface at which a plurality of electrode pads is located, the plurality of electrode pads being connected with the multilevel wiring layer, and a second element surface at a side opposite to the first element surface; a first heat dissipation member located at a region of the first surface of the wiring substrate overlapping the control element; a heat dissipation structure facing the second element surface of the control element, the heat dissipation structure being exposed at the second surface of the wiring substrate; and at least one memory element located at a region of the first surface of the wiring substrate not overlapping the control element, the at least one memory element being connected with the multilevel wiring layer, the multilevel wiring layer including a signal pattern electrically connecting the control element with the memory element or an external connection terminal, and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein at least one memory element is further provided at a region of the second surface of the wiring substrate not overlapping the control element, and the at least one memory element is connected with the multilevel wiring layer. ### Claim 3 (depends on 2) The memory device according to claim 2, wherein the heat dissipation structure includes a third heat dissipation member protruding from the second surface of the wiring substrate. ### Claim 4 (depends on 3) A memory device module, comprising: a plurality of the memory devices according to claim 3; and a cooling member, the plurality of memory devices being arranged so that the first heat dissipation member of an other memory device among adjacent memory devices of the plurality of memory devices is connected to the third heat dissipation member of the heat dissipation structure of one memory device among the adjacent memory devices, the third heat dissipation member being exposed from the wiring substrate of the heat dissipation structure, the cooling member extending along an arrangement direction of the plurality of memory devices, the cooling member being connected to side surfaces of the first heat dissipation members and side surfaces of the third heat dissipation members. ### Claim 5 (depends on 1) The memory device according to claim 1, wherein the plurality of electrode pads of the control element include a power supply pad and a ground pad, a power supply potential being applied to the power supply pad, a ground potential being applied to the ground pad, and the heat dissipation conductor pattern includes at least one of: a power supply pattern connected with the power supply pad, the power supply pattern having a greater width than the signal pattern; or a ground pattern connected with the ground pad, the ground pattern having a greater width than the signal pattern. ### Claim 6 (depends on 5) The memory device according to claim 5, wherein at least one memory element is further provided at a region of the second surface of the wiring substrate not overlapping the control element, and the at least one memory element is connected with the multilevel wiring layer. ### Claim 7 (depends on 1) The memory device according to claim 1, wherein a metal pattern is located at the first element surface of the control element, the metal pattern is not connected with the plurality of electrode pads of the control element or the signal pattern of the wiring substrate, and the metal pattern is connected with the heat dissipation conductor pattern. ### Claim 8 (depends on 7) The memory device according to claim 7, wherein at least one memory element is further provided at a region of the second surface of the wiring substrate not overlapping the control element, and the at least one memory element is connected with the multilevel wiring layer. ### Claim 9 (depends on 1) The memory device according to claim 1, wherein the heat dissipation structure includes: a metal layer located at the second element surface of the control element, and a plurality of heat vias connected to the metal layer, and the plurality of heat vias is more numerous than the plurality of electrode pads. ### Claim 10 (depends on 1) The memory device according to claim 1, wherein the heat dissipation structure includes a second heat dissipation member embedded in the wiring substrate. ### Claim 11 (depends on 1) A memory device module, comprising: a plurality of the memory devices according to claim 1; and a cooling member, the plurality of memory devices being arranged so that the first heat dissipation member of an other memory device among adjacent memory devices of the plurality of memory devices is connected to a surface of the heat dissipation structure of one memory device among the adjacent memory devices, the surface being exposed from the wiring substrate, the cooling member extending along an arrangement direction of the plurality of memory devices, the cooling member being connected to side surfaces of the first heat dissipation members.