# US 12,009,277 B2 · Semiconductor package

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- Number: US 12,009,277 B2
- Document ID: US12009277B2
- Status: Granted
- Kind: B2
- Application number: 17/866,866
- Filed: 2022-07-18
- Published: 2022-11-03
- Granted: 2024-06-11
- Earliest claimed: 2019-06-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong Kyu Kim; Jung-Ho Park; Jong Youn Kim; Yeon Ho Jang; Jae Gwon Jang
- Web page: https://patentgrep.com/patent/US12009277B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/77: Auxiliary members characterised by their shape
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/10: Arrangements for heating
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 90/00: Package configurations
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

## Claims

### Claim 1

A semiconductor package, comprising:
a first semiconductor chip and a second semiconductor chip on a substrate, the first and second semiconductor chips being equal in thickness such that uppermost faces of the first and second semiconductor chips are located at a same height from the substrate;
a barrier layer having an opening that exposes a first portion of the uppermost face of the first semiconductor chip, the barrier layer being in contact with a second portion of the uppermost face of the first semiconductor chip not exposed by the opening and an entirety of the uppermost face of the second semiconductor chip and; and
a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a thickness of the heat transfer part is greater than a thickness of the barrier layer.

### Claim 3 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the heat transfer part on the first semiconductor chip has substantially the same thickness as the heat transfer part on the barrier layer.

### Claim 4 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the heat transfer part on the first semiconductor chip is thicker than the heat transfer part on the barrier layer.

### Claim 5 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the barrier layer includes a photosensitive polymer.

### Claim 6 (depends on 1)

The semiconductor package as claimed in claim 1, wherein:
the heat transfer part includes an adhesive metal layer and a heat transfer material layer on an upper face of the adhesive metal layer, and
an undercut region is formed at an end of the adhesive metal layer.

### Claim 7 (depends on 1)

The semiconductor package as claimed in claim 1, wherein:
the heat transfer part includes an adhesive metal layer and a heat transfer material layer on an upper face of the adhesive metal layer, and
a portion of the heat transfer part is in contact with the first portion of the uppermost face of the first semiconductor chip.

### Claim 8 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the first semiconductor chip is a logic chip, the second semiconductor chip is a memory chip, and the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the substrate.

### Claim 9 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising a heat slug on the heat transfer part.

### Claim 10

A semiconductor package, comprising:
a first semiconductor chip on a substrate, the first semiconductor chip having an uppermost face located at a first height from the substrate;
a second semiconductor chip on the substrate, the second semiconductor chip having an uppermost face located at the first height from the substrate such that the uppermost faces of the first and second semiconductor chips are located at a same level;
a heat transfer part on the first semiconductor chip and the second semiconductor chip, the heat transfer part being in contact with the uppermost face of the first semiconductor chip, and not contacting the second semiconductor chip; and
a heat slug in contact with at least a portion of the heat transfer part.

### Claim 11 (depends on 10)

The semiconductor package as claimed in claim 10, wherein a thickness of the heat transfer part on the first semiconductor chip is substantially the same as a thickness of the heat transfer part on the second semiconductor chip.

### Claim 12 (depends on 11)

The semiconductor package as claimed in claim 11, wherein the heat slug is in contact with the heat transfer part on the first semiconductor chip and not in contact with the heat transfer part on at least a portion of the second semiconductor chip.

### Claim 13 (depends on 10)

The semiconductor package as claimed in claim 10, wherein the heat transfer part on the first semiconductor chip is thicker than the heat transfer part on the second semiconductor chip.

### Claim 14 (depends on 10)

The semiconductor package as claimed in claim 10, further comprising a barrier layer between the second semiconductor chip and the heat transfer part.

### Claim 15 (depends on 14)

The semiconductor package as claimed in claim 14, wherein the heat transfer part is thicker than the barrier layer.

### Claim 16 (depends on 10)

The semiconductor package as claimed in claim 10, wherein an undercut region is formed at an end of the heat transfer part.

### Claim 17 (depends on 10)

The semiconductor package as claimed in claim 10, wherein the heat slug extends from one side of the substrate to the other side of the substrate.

### Claim 18

A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate;
a second semiconductor chip on the substrate, an uppermost face of the second semiconductor chip being located at a same height as an uppermost face of the first semiconductor chip;
a molding part on the substrate, wrapping the first semiconductor chip and the second semiconductor chip, and exposing the uppermost face of the first semiconductor chip and the uppermost face of the second semiconductor chip, an uppermost face of the molding part being located at the same height as the uppermost face of the first semiconductor chip;
a barrier layer including an opening through which a first portion of the uppermost face of the first semiconductor chip is exposed, the barrier layer covering the second semiconductor chip and a second portion of the uppermost face of the first semiconductor chip not exposed by the opening; and
a heat transfer part on the barrier layer and in direct contact with the first portion of the uppermost face of the first semiconductor chip exposed by the opening.

### Claim 19 (depends on 18)

The semiconductor package as claimed in claim 18, further comprising a heat slug on the heat transfer part.

### Claim 20 (depends on 18)

The semiconductor package as claimed in claim 18, wherein:
the second semiconductor chip has a structure in which a plurality of memory chips is stacked, and
each memory chip is thinner than the first semiconductor chip.