# US 12,009,274 B2 · Semiconductor package including thermal exhaust pathway

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,274 B2
- Document ID: US12009274B2
- Status: Granted
- Kind: B2
- Application number: 17/358,149
- Filed: 2021-06-25
- Published: 2022-08-18
- Granted: 2024-06-11
- Earliest claimed: 2021-02-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Eungkyu Kim; Kyounglim Suk
- Web page: https://patentgrep.com/patent/US12009274B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/611: {for connecting multiple chips together}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/778: {in encapsulations}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/014: {using batch processing}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/965: {Providing thermal transfer}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

## Claims

### Claim 1

A semiconductor package comprising:
a wiring structure including signal wiring and a heat transfer wiring spaced apart from the signal wiring;
an active chip on the wiring structure;
a signal terminal disposed between the wiring structure and the active chip;
a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring;
a passive chip on the wiring structure;
a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring; and
a heat spreader on the passive chip,
wherein the passive chip is an electrically inactive dummy chip, and
wherein the heat transfer wiring is a single wiring in the wiring structure, and the plurality of first heat transferring terminals and the plurality of second heat transferring terminals are commonly connected to the single wiring.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein the passive chip has a first thickness greater than a second thickness of the active chip.

### Claim 3 (depends on 1)

The semiconductor package according to claim 1, wherein vertical spacing between the passive chip and the heat spreader is less than vertical spacing between the active chip and the heat spreader.

### Claim 4 (depends on 1)

The semiconductor package according to claim 1, wherein the signal terminal, the first heat transferring terminal, and the second heat transferring terminal includes at least one of a solder ball, a conductive bump, an under bump metallurgy (UBM), a conductive pillar, a conductive lead, and a conductive pin.

### Claim 5 (depends on 1)

The semiconductor package according to claim 1, further comprising:
a first encapsulant between the wiring structure and the active chip and between the wiring structure and the passive chip,
wherein the first encapsulant includes an underfill material including a filler and a resin.

### Claim 6 (depends on 1)

The semiconductor package according to claim 1, further comprising:
a second encapsulant covers exposed portions of the wiring structure and exposed portions of side surfaces of the passive chip.

### Claim 7 (depends on 6)

The semiconductor package according to claim 6, wherein the second encapsulant covers exposed side surface of the active chip.

### Claim 8 (depends on 6)

The semiconductor package according to claim 6, wherein the second encapsulant extends between the exposed portions of the wiring structure and the heat spreader.

### Claim 9 (depends on 1)

The semiconductor package according to claim 1, further comprising:
a thermal interface material layer between the passive chip and the heat spreader.

### Claim 10 (depends on 9)

The semiconductor package according to claim 9, wherein the thermal interface material layer directly contacts an upper surface of the passive chip.

### Claim 11 (depends on 9)

The semiconductor package according to claim 9, wherein the thermal interface material layer directly contacts an upper surface of the active chip.

### Claim 12 (depends on 9)

The semiconductor package according to claim 9, wherein the thermal interface material layer extends between the active chip and the heat spreader.

### Claim 13 (depends on 1)

The semiconductor package according to claim 1, further comprising:
a through electrode extending through the passive chip between the second heat transferring terminal and the heat spreader.

### Claim 14

A semiconductor package comprising:
a wiring structure including signal wiring and a heat transfer wiring;
an active chip on the wiring structure and connected to the signal wiring and the heat transfer wiring;
a passive chip on the wiring structure and connected to the heat transfer wiring; and
a heat spreader on the passive chip,
wherein the passive chip is an electrically inactive dummy chip, and
wherein the heat transfer wiring is a single wiring in the wiring structure, and wherein the active chip and the passive chip are commonly connected to the single wiring.

### Claim 15 (depends on 14)

The semiconductor package according to claim 14, wherein the wiring structure includes at least one of a redistribution layer, a printed circuit board, an interposer substrate, a logic chip, a buffer chip, a controller chip, an application processor chip, an interposer chip, a volatile memory chip and a non-volatile memory chip.

### Claim 16

A semiconductor package comprising:
a redistribution layer including signal wiring and a heat transfer wiring;
an active chip on the redistribution layer;
a signal terminal between the redistribution layer and the active chip;
a first heat transferring terminal between the redistribution layer and the active chip and connected to the heat transfer wiring;
a passive chip on the redistribution layer;
a second heat transferring terminal disposed between the redistribution layer and the passive chip and connected to the heat transfer wiring;
a heat spreader on the passive chip;
an external terminal on a lower surface of the redistribution layer; and
an encapsulant disposed on the redistribution layer between the active chip and the heat spreader,
wherein the passive chip is an electrically inactive dummy chip, and
wherein the heat transfer wiring is a single wiring in the wiring structure, and wherein the first heat transferring terminal and the second heat transferring terminal are commonly connected to the single wiring.

### Claim 17 (depends on 16)

The semiconductor package according to claim 16, further comprising:
a thermal interface material layer between the passive chip and the heat spreader, and between the active chip and the heat spreader.

### Claim 18 (depends on 17)

The semiconductor package according to claim 17, wherein the thermal interface material layer directly contacts the passive chip.

### Claim 19 (depends on 16)

The semiconductor package according to claim 16, wherein the encapsulant includes an epoxy molding compound.