# US 12,009,272 B2 · Integral redistribution layer for WCSP

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- Number: US 12,009,272 B2
- Document ID: US12009272B2
- Status: Granted
- Kind: B2
- Application number: 17/526,533
- Filed: 2021-11-15
- Published: 2023-05-18
- Granted: 2024-06-11
- Earliest claimed: 2021-11-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Rafael Jose Lizares Guevara
- Web page: https://patentgrep.com/patent/US12009272B2

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/147: {the encapsulations being multilayered}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 72/019: {of bond pads}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer chip scale package (WCSP) includes a substrate including a semiconductor surface including circuitry electrically connected to die bond pads exposed by a passivation layer, and a top dielectric layer over the passivation layer. A dielectric layer bounded (DLB) cavity formed in the top dielectric layer includes a first cavity being a center through-cavity bounded by a second cavity being a partial through-cavity, the DLB cavity is lined with a seed layer. A capping dielectric layer that covers the DLB cavity except for an aperture over the first cavity. A cavity metal that is generally configured as an integral structure of continuous metal material having no interfaces is for filling the DLB cavity to form a metal filled cavity including over the aperture that has an electrical connection to the die bond pads. A solder ball over the cavity metal is positioned over the aperture.

## Claims

### Claim 1

A wafer chip scale package (WCSP), comprising:
a substrate comprising a semiconductor surface including circuitry electrically connected to die bond pads exposed by a passivation layer, further comprising a first dielectric layer over the passivation layer;
a first cavity in the first dielectric layer comprising a center through-cavity bounded by a second cavity comprising a partial through-cavity;
a second dielectric layer that covers the first and second cavities except for an aperture over the second cavity;
a metal filling the first and second cavities and the aperture, the metal being electrically connected to the die bond pads; and
a solder ball on the metal positioned within the aperture.

### Claim 2 (depends on 1)

The WCSP of claim 1, wherein the metal is configured as an integral structure of continuous metal material having no interfaces.

### Claim 3 (depends on 1)

The WCSP of claim 1, wherein a depth of the first cavity is between 5μm and 20 μm, and wherein a thickness of the cavity metal is 10 μm to 50 μm.

### Claim 4 (depends on 1)

The WCSP of claim 1, wherein there is no under-bump metallization (UBM) layer under the solder ball.

### Claim 5 (depends on 1)

The WCSP of claim 1, wherein the aperture is exclusively over the second cavity.

### Claim 6 (depends on 1)

The WCSP of claim 1, wherein the first dielectric layer comprises a polyimide (PI).

### Claim 7 (depends on 1)

The WCSP of claim 1, wherein the metal is part of a redistribution layer (RDL).

### Claim 8 (depends on 1)

The WCSP of claim 1, wherein the metal comprises copper.

### Claim 9 (depends on 1)

The WCSP of claim 1, wherein a seed layer lining the first and second cavities comprises TiW/Cu.

### Claim 10

A method, comprising:
providing a wafer chip scale package (WCSP) including circuitry electrically coupled to die bond pads exposed by a passivation layer, further comprising a first dielectric layer the passivation layer;
forming in the dielectric layer a first cavity comprising a center through-cavity bounded by a second cavity comprising a partial through-cavity;
forming a pattern seed layer that lines the first and second cavities;
forming a second dielectric layer on the first dielectric layer that covers the first and second cavities;
forming an aperture in the second dielectric layer over the second cavity;
plating a metal in the first and second cavities and the aperture; and
positioning a solder ball on the metal in the aperture.

### Claim 11 (depends on 10)

The method of claim 10, wherein the plating consists of a single plating step, and wherein the metal is configured as an integral structure of continuous metal material having no interfaces.

### Claim 12 (depends on 10)

The method of claim 10, wherein laser ablation is used to form the aperture, the laser ablation comprising a two-step laser ablation process including a first ablation step for forming the first cavity and a second ablation step for forming the second cavity.

### Claim 13 (depends on 10)

The method of claim 10, wherein the secondcapping dielectric layer comprises a polyamide (PI).

### Claim 14 (depends on 10)

The method of claim 10, wherein a depth of the first cavity is between 5 μm and 20 μm.

### Claim 15 (depends on 14)

The method of claim 14, wherein a thickness of the cavity metal is 10 μm to 50 μm.

### Claim 16 (depends on 10)

The method of claim 10, wherein there is no under-bump metallization (UBM) layer under the solder ball.

### Claim 17 (depends on 10)

The method of claim 10, wherein the aperture is exclusively over the second cavity.

### Claim 18 (depends on 10)

The method of claim 10, wherein the top dielectric layer comprises a polyimide (PI).

### Claim 19 (depends on 10)

The method of claim 10, wherein the metal is part of a redistribution layer (RDL).

### Claim 20 (depends on 10)

The method of claim 10, wherein the forming of the patterned seed layer comprises chemical mechanical planarization (CMP) to pattern the seed layer.

### Claim 21

A wafer chip scale package (WCSP), comprising:
a substrate comprising a semiconductor surface including circuitry electrically connected to die bond pads exposed by a passivation layer, further comprising a dielectric layer covering the passivation layer;
a first cavity through the dielectric layer bounded by a second cavity partially through the dielectric layer;
a second dielectric layer covering the dielectric layer except for an aperture over the second cavity;
a metal filling the first and second cavities and the aperture and contacting at least one of the die bond pads; and
a solder ball on the metal within the aperture.

### Claim 22 (depends on 21)

The WCSP of claim 21, wherein the metal is at least a part of a redistribution layer.

### Claim 23 (depends on 21)

The WCSP of claim 21, wherein the dielectric layer, the first cavity, the second cavity and the second dielectric layer form a dielectric layer bounded (DLB) cavity.

### Claim 24 (depends on 21)

The WCSP of claim 21, wherein the aperture is exclusively over the second cavity.