# US 12,009,271 B2 · Protruding SN substrate features for epoxy flow control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,271 B2 - Document ID: US12009271B2 - Status: Granted - Kind: B2 - Application number: 16/511,360 - Filed: 2019-07-15 - Published: 2021-01-21 - Granted: 2024-06-11 - Earliest claimed: 2019-07-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Edvin Cetegen; Jacob Vehonsky; Nicholas S. Haehn; Thomas Heaton; Steve S. Cho; Rahul Jain; Tarek Ibrahim; Antariksh Rao Pratap Singh; Nicholas Neal; Sergio Chan Arguedas; Vipul Mehta - Web page: https://patentgrep.com/patent/US12009271B2 ## CPC - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 72/073: {of die-attach connectors} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/072: {of bump connectors} - H10W 72/07236: {Soldering or alloying} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/354: {comprising polymers} - H10W 72/387: {Flow barriers} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature. ## Claims ### Claim 1 An electronic package, comprising: a package substrate; a plurality of interconnects on the package substrate; a die coupled to the package substrate by the plurality of interconnects, the die having a footprint; a flow control feature on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package, wherein the flow control feature comprises a plurality of substantially parallel lines, and wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die; and an underfill surrounding the plurality of interconnects and in contact with the flow control feature. ### Claim 2 (depends on 1) The electronic package of claim 1, wherein the plurality of substantially parallel lines run in a direction substantially parallel to a direction of flow of the underfill. ### Claim 3 (depends on 1) The electronic package of claim 1, wherein the plurality of substantially parallel lines run in a direction substantially orthogonal to a direction of flow of the underfill. ### Claim 4 (depends on 1) The electronic package of claim 1, wherein the flow control feature comprises first lines and second lines, wherein the first lines are substantially orthogonal to the second lines. ### Claim 5 (depends on 1) The electronic package of claim 1, wherein a first flow control feature is adjacent to a first edge of the die and a second flow control feature is adjacent to a second edge of the die, wherein the first edge is opposite the second edge. ### Claim 6 (depends on 5) The electronic package of claim 5, wherein the first flow control feature is substantially similar to the second flow control feature. ### Claim 7 (depends on 5) The electronic package of claim 5, wherein the first flow control feature is different than the second flow control feature. ### Claim 8 (depends on 1) The electronic package of claim 1, further comprising: a second die adjacent to the first die, wherein the flow control feature is positioned between the first die and the second die. ### Claim 9 (depends on 1) The electronic package of claim 1, further comprising: an underfill source region on the package substrate, wherein the flow control feature comprises a plurality of substantially parallel lines that extend from the underfill source region to an edge of the die. ### Claim 10 (depends on 1) The electronic package of claim 1, wherein the flow control feature comprises a ring around a perimeter of the die. ### Claim 11 (depends on 10) The electronic package of claim 10, wherein the underfill contacts an interior sidewall of the ring. ### Claim 12 (depends on 11) The electronic package of claim 11, wherein the underfill further contacts a top surface of the ring. ### Claim 13 (depends on 1) The electronic package of claim 1, wherein the flow control feature comprises a pad and solder over the pad. ### Claim 14 (depends on 1) The electronic package of claim 1, wherein the flow control feature comprises the same material composition as the plurality of interconnects. ### Claim 15 A package substrate, comprising: a plurality of dielectric layers; a plurality of pads arranged in an array over the plurality of dielectric layers; a plurality of bumps, wherein each bump is over a different one of the plurality of pads; a flow control feature over the plurality of dielectric layers, wherein the flow control feature comprises one or more lines, and wherein the flow control feature comprises the same material as the plurality of bumps; and a die having a footprint, wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die. ### Claim 16 (depends on 15) The package substrate of claim 15, wherein the one or more lines of the flow control feature run substantially parallel to an edge of the array. ### Claim 17 (depends on 15) The package substrate of claim 15, wherein the one or more lines of the flow control feature run substantially orthogonal to an edge of the array. ### Claim 18 (depends on 15) The package substrate of claim 15, wherein the plurality of pads are arranged in a first array and a second array, and wherein the flow control feature is positioned between the first array and the second array. ### Claim 19 (depends on 15) The package substrate of claim 15, wherein the plurality of bumps comprise a solder. ### Claim 20 An electronic system, comprising: a board; an electronic package electrically coupled to the board, wherein the electronic package comprises a plurality of interconnects arranged in an array and a flow control feature adjacent to the array, wherein the flow control feature comprises a plurality of lines, and wherein the plurality of lines run substantially parallel to an edge of the array or substantially orthogonal to an edge of the array; a die electrically coupled to the electronic package by the plurality of interconnects, the die having a footprint, wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die; and an underfill material surrounding the plurality of interconnects and in contact with the flow control feature. ### Claim 21 (depends on 20) The electronic system of claim 20, wherein the flow control feature is electrically isolated from circuitry of the electronic system. ### Claim 22 (depends on 20) The electronic system of claim 20, wherein the flow control feature comprises a solder. ### Claim 23 An electronic package, comprising: a package substrate; a plurality of interconnects on the package substrate; a die coupled to the package substrate by the plurality of interconnects, the die having a footprint; a flow control feature on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package, wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die, wherein a first flow control feature is adjacent to a first edge of the die and a second flow control feature is adjacent to a second edge of the die, and wherein the first edge is opposite the second edge; and an underfill surrounding the plurality of interconnects and in contact with the flow control feature. ### Claim 24 An electronic package, comprising: a package substrate; a plurality of interconnects on the package substrate; a die coupled to the package substrate by the plurality of interconnects, the die having a footprint; a flow control feature on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package, and wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die; an underfill surrounding the plurality of interconnects and in contact with the flow control feature; and an underfill source region on the package substrate, wherein the flow control feature comprises a plurality of substantially parallel lines that extend from the underfill source region to an edge of the die. ### Claim 25 An electronic package, comprising: a package substrate; a plurality of interconnects on the package substrate; a die coupled to the package substrate by the plurality of interconnects, the die having a footprint; a flow control feature on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package, wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die, and wherein the flow control feature comprises a pad and solder over the pad; and an underfill surrounding the plurality of interconnects and in contact with the flow control feature. ### Claim 26 An electronic package, comprising: a package substrate; a plurality of interconnects on the package substrate; a die coupled to the package substrate by the plurality of interconnects, the die having a footprint; a flow control feature on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package, and wherein the flow control feature is continuous from a location within the footprint of the die to a location outside of the footprint of the die, wherein the flow control feature comprises the same material composition as the plurality of interconnects; and an underfill surrounding the plurality of interconnects and in contact with the flow control feature.