# US 12,009,269 B2 · Virtual metrology for feature profile prediction in the production of memory devices

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- Number: US 12,009,269 B2
- Document ID: US12009269B2
- Status: Granted
- Kind: B2
- Application number: 17/725,695
- Filed: 2022-04-21
- Published: 2022-12-29
- Granted: 2024-06-11
- Earliest claimed: 2021-06-28
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Cheng-Chung Chu; Masaaki Higashitani; Yusuke Ikawa; Seyyed Ehsan Esfahani Rashidi; Kei Samura; Tsuyoshi Sendoda; Yanli Zhang
- Web page: https://patentgrep.com/patent/US12009269B2

## CPC

- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- G11C 29/44: Indication or identification of errors, e.g. for repair
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/238: {comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement}
- H10B 43/10: characterised by the top-view layout
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

## Claims

### Claim 1

A method, comprising:
receiving a first plurality of an integrated circuit as first test samples, the integrated circuit comprising a plurality of circuitry layers formed on a substrate;
performing one or more first tests on the first test samples to determine a corresponding one or more metrology data values for each of the first test samples;
performing one or more second tests on the first plurality of the integrated circuit, the one or more second tests including determining values for electrical properties of a first subset of the circuitry layers;
performing a machine learning process to determine a correlation between the metrology data values and results of the one or more second tests;
receiving a second plurality of the integrated circuit;
determining, for the second plurality of the integrated circuit, values for the electrical properties of a first plurality of the circuitry layers, the first plurality of the circuitry layers including circuitry layers other than the first subset of the circuitry layers; and
interpolating metrology data values for the first plurality of the circuitry layers of the second plurality of the integrated circuit from the correlation and results of the values for the electrical properties of the first plurality of the circuitry layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of circuitry layers include a plurality of layers of word lines and the electrical properties of the circuitry layers comprise electrical properties of the word lines.

### Claim 3 (depends on 2)

The method of claim 2, wherein the electrical properties of the word lines include resistance-capacitance (RC) values for the word lines.

### Claim 4 (depends on 3)

The method of claim 3, wherein determining the RC values for the electrical properties of the word lines of the circuitry layers comprises:
applying a voltage to each of the word lines; and
determining for each of the word lines a time for voltage level on the word line to reach a specified voltage level in response to the application of the voltage.

### Claim 5 (depends on 2)

The method of claim 2, wherein determining for the second plurality of the integrated circuit values for the electrical properties of the first plurality of the circuitry layers includes determining electrical properties of all of the word lines of all of the layers of word lines.

### Claim 6 (depends on 2)

The method of claim 2, wherein the integrated circuit further comprises a plurality of memory holes extending vertically through layers of word lines, and
wherein the interpolated metrology for the first plurality of the circuitry layers of the second plurality of the integrated circuit includes profiled for the memory holes.

### Claim 7 (depends on 1)

The method of claim 1, wherein determining for the second plurality of the integrated circuit values for the electrical properties of the first plurality of the circuitry layers is performed as part of a die sort process.

### Claim 8 (depends on 1)

The method of claim 1, wherein one or more of the first tests are performed as part of a die sort test process.

### Claim 9 (depends on 1)

The method of claim 1, wherein one or more of the first tests are performed as part of an inline test process during fabrication of the first test samples.

### Claim 10 (depends on 1)

The method of claim 1, wherein one or more of the second tests are performed as part of a die sort test process.

### Claim 11 (depends on 1)

The method of claim 1, wherein one or more of the second tests are performed as part of an inline test process during fabrication of the first test samples.

### Claim 12 (depends on 1)

The method of claim 1, further comprising:
receiving a model of the electrical properties of the integrated circuit, wherein the machine learning process uses the model in determining the correlation between the metrology data values and results of the one or more second tests.

### Claim 13 (depends on 1)

The method of claim 1, wherein one or more of the first tests include:
determining critical dimension data by an electron microscope.

### Claim 14 (depends on 1)

The method of claim 1, wherein one or more of the first tests include:
determining optical critical dimension data.

### Claim 15 (depends on 14)

The method of claim 14, wherein the integrated circuit further comprises one or more trenches extending vertically through layers of the integrated circuit and the optical critical dimension data includes critical dimension data for the trenches.

### Claim 16 (depends on 1)

The method of claim 1, wherein performing the machine learning process comprises:
selecting a machine learning model.

### Claim 17 (depends on 1)

The method of claim 1, wherein receiving the first plurality of the integrated circuit and receiving the second plurality of the integrated circuit respectively comprise fabricating the first plurality of the integrated circuit and fabricating the second plurality of the integrated circuit.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first plurality of the integrated circuit and the second plurality of the integrated circuit are fabricated using a first set of processing parameters and the method further comprises:
based the interpolated metrology data values, adjusting the first set of processing parameters; and
fabricating the integrated circuit using the adjusted first set of processing parameters.

### Claim 19

A method, comprising:
fabricating a plurality of an integrated circuit using a first set of processing parameters, the integrated circuit comprising a plurality of circuitry layers formed on a substrate;
selecting a first plurality of the integrated circuit as first test samples;
performing one or more first tests on the first test samples to determine a corresponding one or more metrology data values for each of the first test samples;
performing one or more second tests on the first plurality of the integrated circuit, the one or more second tests including determining values for electrical properties of a first subset of the circuitry layers;
performing a machine learning process to determine a correlation between the metrology data values and results of the one or more second tests;
selecting a second plurality of the integrated circuit;
determining, for the second plurality of the integrated circuit, values for the electrical properties of a first plurality of the circuitry layers, the first plurality of the circuitry layers including circuitry layers other than the first subset of the circuitry layers;
interpolating metrology data values for the first plurality of the circuitry layers of the second plurality of the integrated circuit from the correlation and results of the values for the electrical properties of the first plurality of the circuitry layers;
based the interpolated metrology data values, adjusting the processing parameters; and
fabricating the integrated circuit using the adjusted processing parameters.

### Claim 20

A system, comprising:
one or more processors, the one or more processors configured to:
receive results of one or more first tests on a plurality of first test samples from a first plurality of an integrated circuit, the integrated circuit comprising a plurality of circuitry layers formed on a substrate;
determine from the one or more first tests a corresponding one or more metrology data values for each of the first test samples;
receive results of one or more second tests on the first test samples of the integrated circuit, the one or more second tests including determining values for electrical properties of a first subset of the circuitry layers;
perform a machine learning process to determine a correlation between the metrology data values and results of the one or more second tests;
receive, for a second plurality of the integrated circuit, values for the electrical properties of a first plurality of the circuitry layers, the first plurality of the circuitry layers including circuitry layers other than the first subset of the circuitry layers; and
interpolate metrology data values for the first plurality of the circuitry layers of the second plurality of the integrated circuit from the correlation and results of the values for the electrical properties of the first plurality of the circuitry layers.