# US 12,009,268 B2 · Semiconductor device and fabrication method for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,009,268 B2 - Document ID: US12009268B2 - Status: Granted - Kind: B2 - Application number: 18/352,285 - Filed: 2023-07-14 - Published: 2023-11-16 - Granted: 2024-06-11 - Earliest claimed: 2019-06-17 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Motoyoshi Kubouchi; Kosuke Yoshida; Soichi Yoshida; Koh Yoshikawa; Nao Suganuma - Web page: https://patentgrep.com/patent/US12009268B2 ## CPC - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes} - H10D 8/422: {PN diodes having the PN junctions in mesas} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/103: {for increasing or controlling the breakdown voltage of reverse-biased devices} - H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/53: the imperfections being within the semiconductor body - H10D 62/60: Impurity distributions or concentrations - H10D 62/605: {Planar doped, e.g. atomic-plane doped or delta-doped} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 84/617: {Combinations of vertical BJTs and only diodes} - H10P 30/20: into semiconductor materials, e.g. for doping - H10P 30/204: {into Group IV semiconductors} - H10P 30/208: {of electrically inactive species} - H10P 30/214: {Recoil-implantation} - H10P 32/171: {being group IV material} - H10P 32/18: {Diffusion lifetime killers} - H10P 95/90: Thermal treatments, e.g. annealing or sintering - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region. ## Claims ### Claim 1 A semiconductor device comprising: a plurality of trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate; a first lower surface region of a first conductivity type provided in at least a part of a lower surface of the semiconductor substrate; a base region of a second conductivity type provided on the upper surface side of the semiconductor substrate; a first region of the first conductivity type provided in the semiconductor substrate and disposed between the base region and the first lower surface region in a depth direction of the semiconductor substrate; a first upper surface region of the first conductivity type provided on an upper surface of the semiconductor substrate; and a first bottom region of the second conductivity type provided in the semiconductor substrate and disposed continuously in the first direction such that the first bottom region is in contact with bottom portions of the plurality of trench portions, wherein in a cross section that (i) is along the first direction and perpendicular to the upper surface and the lower surface of the semiconductor substrate and (ii) passes through the first lower surface region, one end portion of the first bottom region in the first direction locates directly above the first lower surface region in the depth direction. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the cross section passes through the first upper surface region. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, further comprising: a second upper surface region of the second conductivity type that is provided on the upper surface of the semiconductor substrate and has a doping concentration higher than a doping concentration of the base region, wherein the first upper surface region has a doping concentration higher than a doping concentration of the first region. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, further comprising: an edge terminal structure portion provided, in a top view, on a side of end sides of the semiconductor device; and a well region of the second conductivity type disposed, in the top view, between the base region and the edge terminal structure portion, wherein an other end portion of the first bottom region in the first direction is separated away from the well region. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the first bottom region is electrically floating. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the edge terminal structure portion includes a plurality of guard rings. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, further comprising: a second lower surface region of the second conductivity type disposed in at least a part of the lower surface of the semiconductor substrate. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, further comprising: a diode portion that includes the first lower surface region; and a transistor portion that includes the second lower surface region, wherein the first bottom region is provided across the transistor portion and the diode portion. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the other end portion of the first bottom region faces the well region and is located in the transistor portion, and the one end portion of the first bottom region faces opposite to the well region and is located in the diode portion. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein each of the plurality of trench portions includes a linear part extending in a second direction substantially perpendicular to the first direction in the top view, and the diode portion and the transistor portion each have a longitudinal side in the second direction. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the diode portion and the transistor portion are alternately arranged in the first direction in the top view. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of trench portions include one or more gate trench portions and one or more dummy trench portions, and the first bottom region is disposed continuously in the first direction such that the first bottom region is in contact with bottom portions of the one or more gate trench portions and the one or more dummy trench portions. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, further comprising: an accumulation region of the first conductivity type disposed between the base region and the first bottom region in the depth direction. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the accumulation region has a doping concentration higher than a doping concentration of the first region and is in contact with an upper surface of the first bottom region. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, further comprising: a buffer region of the first conductivity type disposed between the first region and the first lower surface region in the depth direction. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, further comprising: a second bottom region of the second conductivity type in contact with a lower surface of the first bottom region. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein in the cross section, the one end portion of the first bottom region in the first direction extend outside of corresponding end portion of the second bottom region in the first direction. ### Claim 18 (depends on 16) The semiconductor device according to claim 16, wherein a doping concentration of the second bottom region is lower than a doping concentration of the first bottom region. ### Claim 19 (depends on 16) The semiconductor device according to claim 16, wherein a doping concentration of the second bottom region is the same as a doping concentration of a bulk doping region of the semiconductor substrate. ### Claim 20 (depends on 1) The semiconductor device according to claim 1, wherein a donor concentration of the first region is higher than a doping concentration of a bulk doping region of the semiconductor substrate.