# US 12,009,267 B2 · Nanosheet device with different gate lengths in same stack

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,267 B2
- Document ID: US12009267B2
- Status: Granted
- Kind: B2
- Application number: 17/203,489
- Filed: 2021-03-16
- Published: 2022-09-22
- Granted: 2024-06-11
- Earliest claimed: 2021-03-16
- Assignees: NXP B.V.
- Applicants: NXP B.V.
- Inventors: Tushar Praful Merchant; Mark Douglas Hall; Anirban Roy
- Web page: https://patentgrep.com/patent/US12009267B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 50/242: {of Group IV materials}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

## Claims

### Claim 1

A method for forming a semiconductor device comprising:
providing a stack of alternating semiconductor layers on a substrate, the stack comprising a plurality of first semiconductor layers interspersed in alternating fashion with a plurality of second semiconductor layers;
selectively etching the stack of alternating semiconductor layers to form a transistor stack on the substrate, where the transistor stack comprises a top portion of etched alternating semiconductor layers and a bottom portion of etched alternating semiconductor layers; and
processing the transistor stack to form a first set of gate electrode structures having a first gate length dimension between a first subset of the plurality of first semiconductor layers and to form a second set of gate electrode structures having a second, shorter gate length dimension between a second subset of the plurality of first semiconductor layers, where the second set of gate electrode structures is formed over the first set of gate electrode structures in the transistor stack, where processing the transistor stack comprises:
processing the bottom portion of etched alternating semiconductor layers in the transistor stack to form first remnant second semiconductor layers having the first gate length dimension; and then subsequently
processing the top portion of etched alternating semiconductor layers in the transistor stack to form second remnant second semiconductor layers having the second, shorter gate length dimension; and then
forming planarized epitaxial semiconductor regions adjacent to the bottom and top portions of the etched alternating semiconductor layers; and then
partially etching the planarized epitaxial semiconductor regions to form first epitaxial source/drain semiconductor regions adjacent to the bottom portion of the etched alternating semiconductor layers which expose the top portion of the etched alternating semiconductor layers; and then
forming a directional oxide layer to cover the first epitaxial source/drain semiconductor regions; and then
forming second epitaxial semiconductor regions adjacent to the top portion of the etched alternating semiconductor layers.

### Claim 2 (depends on 1)

The method of claim 1, where each of the plurality of first semiconductor layers comprises a silicon nanosheet layer, and where each of the plurality of second semiconductor layers comprises a silicon germanium nanosheet layer.

### Claim 3 (depends on 1)

The method of claim 1, where the plurality of first semiconductor layers is formed with a first semiconductor material and where the plurality of second semiconductor layers is formed with a second semiconductor material having a different isotropic etch rate from the first semiconductor material.

### Claim 4 (depends on 1)

The method of claim 1, where processing the transistor stack comprises:
selectively removing the first remnant second semiconductor layers and second remnant second semiconductor layers, respectively, from the bottom and top portions of the transistor stack, thereby forming first gate electrode openings in the bottom portion of the transistor stack and second gate electrode openings in the top portion of the transistor stack; and
sequentially depositing a conformal gate dielectric layer and conformal conductive gate layer in the first and second gate electrode openings, thereby forming (a) the first set of gate electrode structures which replace the first remnant second semiconductor layers in the bottom portion of the transistor stack, and (b) the second set of gate electrode structures which replace the second remnant second semiconductor layers in the top portion of the transistor stack.

### Claim 5 (depends on 1)

The method of claim 1, where providing the stack of alternating semiconductor layers on a substrate comprises:
epitaxially growing alternating first and second semiconductor layers on the substrate to form a bottom portion of the stack;
forming a barrier insulator layer on the bottom portion of the stack; and
epitaxially growing alternating first and second semiconductor layers on the barrier insulator layer to form a top portion of the stack.

### Claim 6

A method for forming a semiconductor device comprising:
providing a nanosheet stack on a substrate comprising a bottom superlattice structure and a top superlattice structure separated from one another by a barrier insulator layer, where each of the bottom and top superlattice structures comprises alternating silicon and silicon germanium nanosheet layers;
selectively etching the nanosheet stack to form a nanosheet transistor stack on the substrate;
processing the nanosheet transistor stack to form first remnant silicon germanium nanosheet layers in at least the bottom superlattice structure having a first gate length dimension; and then subsequently
processing the nanosheet transistor stack to form second remnant silicon germanium nanosheet layers in the top superlattice structure having a second gate length dimension that is shorter than the first gate length dimension;
forming planarized epitaxial semiconductor regions adjacent to the bottom superlattice structure and a top superlattice structure;
partially etching the planarized epitaxial semiconductor regions to form first epitaxial source/drain semiconductor regions adjacent to the bottom superlattice structure which expose the top superlattice structure;
forming a directional insulator layer to cover the first epitaxial source/drain semiconductor regions;
forming second epitaxial semiconductor regions adjacent to the top superlattice structure,
where the first and second epitaxial source/drain semiconductor regions are electrically isolated from one another by an insulating directional insulator layer; and
selectively processing the nanosheet transistor stack to simultaneously form (a) bottom gate electrodes which replace the first remnant silicon germanium nanosheet layers in the bottom superlattice structure, thereby forming a bottom nanosheet transistor comprising the bottom gate electrodes having the first gate length dimension, the silicon nanosheet layers from the bottom superlattice structure, and the first epitaxial source/drain semiconductor regions, and (b) top gate electrodes which replace the second remnant silicon germanium nanosheet layers in the top superlattice structure, thereby forming a top nanosheet transistor comprising the top gate electrodes having the second gate length dimension that is shorter than the first gate length dimension, the silicon nanosheet layers from the top superlattice structure, and the second epitaxial source/drain semiconductor regions.

### Claim 7 (depends on 6)

The method of claim 6, where providing the nanosheet stack comprises:
epitaxially growing alternating nanosheet layers of silicon and silicon germanium on the substrate to form the bottom superlattice structure;
forming the barrier insulator layer on the bottom superlattice structure;
forming an epitaxial growth seed layer on the barrier insulator layer; and
epitaxially growing alternating nanosheet layers of silicon and silicon germanium on the seed layer to form the top superlattice structure.

### Claim 8 (depends on 6)

The method of claim 6, where processing the nanosheet transistor stack to form first remnant silicon germanium nanosheet layers comprises:
partially recessing silicon germanium nanosheet layers from peripheral sides of the bottom superlattice structure to form recess cavities which define the first remnant silicon germanium nanosheet layers to have the first gate length dimension; and
filling the recess cavities with one or more dielectric layers to form dielectric spacers on peripheral sides of the bottom superlattice structure.

### Claim 9 (depends on 8)

The method of claim 8, where filling the recess cavities comprises:
depositing a nitride layer on at least the nanosheet transistor stack using a thin film technology; and
etching the nitride layer to form the nitride spacers on peripheral sides of the first remnant silicon germanium nanosheet layers.

### Claim 10 (depends on 6)

The method of claim 6, where processing the nanosheet transistor stack to form second remnant silicon germanium nanosheet layers comprises:
partially recessing silicon germanium nanosheet layers from peripheral sides of the top superlattice structure to form recess cavities which define the second remnant silicon germanium nanosheet layers to have the second gate length dimension; and
filling the recess cavities with one or more dielectric layers to form dielectric spacers on peripheral sides of the top superlattice structure.

### Claim 11 (depends on 6)

The method of claim 6, where selectively processing the nanosheet transistor stack comprises:
selectively etching the first and second remnant silicon germanium nanosheet layers from the nanosheet transistor stack to respectively form first and second gate etch openings in the bottom and top superlattice structures;
conformally depositing one or more dielectric layers in the first and second gate etch openings using a thin film technology; and
conformally depositing one or more conductive layers in the first and second gate etch openings to form bottom and top gate electrodes in the bottom and top superlattice structures.

### Claim 12 (depends on 11)

The method of claim 11, further comprising forming an organic oxide layer over the substrate to protect the first gate electrodes in the bottom superlattice structure while leaving exposed the first gate electrodes in the top superlattice structure.