# US 12,009,266 B2 · Structure for fringing capacitance control

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- Number: US 12,009,266 B2
- Document ID: US12009266B2
- Status: Granted
- Kind: B2
- Application number: 16/718,316
- Filed: 2019-12-18
- Published: 2021-06-24
- Granted: 2024-06-11
- Earliest claimed: 2019-12-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Keng-Yao Chen; Chang-Yun Chang; Ming-Chang Wen
- Web page: https://patentgrep.com/patent/US12009266B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.

## Claims

### Claim 1

A method, comprising:
forming a gate structure on fin structures disposed on a substrate;
forming an opening of substantially constant width in the gate structure between two adjacent fin structures, to divide the gate structure into first and second sections spaced apart by the opening, wherein the opening has a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the substrate, and wherein forming the opening comprises forming a recess in a dielectric layer between the fin structures;
depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening; and
depositing a silicon oxide fill layer in the opening and on the silicon nitride liner, comprising forming an air gap within the silicon oxide fill layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein depositing the silicon nitride liner comprises conformally depositing the silicon nitride liner so that a thickness ratio between the silicon nitride liner and the silicon oxide fill layer ranges between about 1:5 and about 1:9.

### Claim 3 (depends on 1)

The method of claim 1, wherein depositing the silicon oxide comprises depositing the silicon oxide fill layer with a plasma-assisted process at a deposition rate that is adjustable by a plasma power of the plasma-assisted process.

### Claim 4 (depends on 3)

The method of claim 3, wherein depositing the silicon oxide fill layer comprises filling the opening with the silicon oxide fill layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the air gap comprises adjusting a deposition rate of the silicon oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the opening comprises forming the opening with sidewalls having a negative slope along a plane parallel to a width of the gate structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the air gap comprises forming the air gap having a width less than about 3 nm.

### Claim 8

A method, comprising:
forming a plurality of fin field effect transistors (finFETs) that share a gate structure;
removing portions of the gate structure between adjacent fin structures of the plurality of finFETs to form openings, wherein removing portions of the gate structure comprises forming a recess in a dielectric layer between the adjacent fin structures with a vertical depth between about 50 nm and about 100 nm below a top surface of the dielectric layer; and
inserting, into the openings, an insulating material of substantially constant width that electrically isolates the finFETs from one another, wherein inserting the insulating material comprises forming an air gap in the insulating material occupying the opening.

### Claim 9 (depends on 8)

The method of claim 8, wherein the gate structure is a metal gate structure, and wherein removing portions of the gate structure comprises forming a cut between the adjacent fin structures of the plurality finFETs.

### Claim 10 (depends on 8)

The method of claim 8, wherein depositing the one or more dielectric materials comprises depositing one or more of a silicon nitride, a silicon oxide, and a silicon oxy-carbide.

### Claim 11 (depends on 10)

The method of claim 10, wherein depositing the one or more dielectric materials comprises depositing the silicon nitride and the silicon oxide so that a thickness ratio between the silicon nitride and the silicon oxide ranges between about 1:5 and about 1:9.

### Claim 12 (depends on 8)

The method of claim 8, further comprising planarizing a surface of the insulating material using a chemical mechanical polishing (CMP) process.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the air gap occurs below a top surface of the gate structure to prevent exposure of the air gap during the CMP process.

### Claim 14

A method of producing transistors, the method comprising:
forming a plurality of fin structures on a semiconductor substrate;
forming a metal gate structure that wraps around each of the plurality of fin structures; and
replacing portions of the metal gate structure with a low-k dielectric material to electrically isolate the plurality of fin structures from one another, wherein replacing portions of the metal gate structure comprises:
cutting the metal gate structure between, and substantially parallel to, adjacent fin structures in the plurality of fin structures to form cuts with a height to width ratio of about 8:1, the width being in a direction perpendicular to a length of the fin structures and parallel to the semiconductor substrate, wherein the cutting comprises forming a recess in a dielectric layer between fin structures in the plurality of fin structures;
depositing, into the cuts, a multi-layer dielectric stack of substantially constant width, comprising a silicon nitride liner and silicon oxide; and
forming an air gap in the multi-layer dielectric stack within the cuts.

### Claim 15 (depends on 14)

The method of claim 14, wherein replacing portions of the metal gate structure comprises filling the metal gate structure with a silicon oxide based dielectric fill material.

### Claim 16 (depends on 14)

The method of claim 14, wherein depositing the multi-layer dielectric stack comprises conformally depositing the multi-layer dielectric to facilitate the formation of the air gap.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the air gap comprises reducing an effective dielectric constant of the multi-layer dielectric stack to less than about 3.9.

### Claim 18 (depends on 14)

The method of claim 14, wherein cutting the metal gate structure comprises forming a plurality of metal gates that are protected, by the cuts, from oxygen diffusion.

### Claim 19 (depends on 14)

The method of claim 14, wherein cutting the metal gate structure comprises recessing the dielectric layer disposed below the metal gate structure.

### Claim 20 (depends on 14)

The method of claim 14, wherein cutting the metal gate structure forms cuts in a range of about 50 nm to about 100 nm.