# US 12,009,264 B2 · Adjusting work function through adjusting deposition temperature

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- Number: US 12,009,264 B2
- Document ID: US12009264B2
- Status: Granted
- Kind: B2
- Application number: 17/838,785
- Filed: 2022-06-13
- Published: 2022-09-29
- Granted: 2024-06-11
- Earliest claimed: 2020-01-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Yi Lee; Ji-Cheng Chen; Cheng-Lung Hung; Weng Chang; Chi On Chui
- Web page: https://patentgrep.com/patent/US12009264B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/014: {the gate conductors having different materials or different implants}
- C23C 16/34: Nitrides {(C23C16/303 takes precedence)}
- C23C 16/45553: {characterized by the use of precursors specially adapted for ALD}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/834: {comprising FinFETs}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. After the recessing, a portion of a semiconductor material between the isolation region protrudes higher than top surfaces of the isolation regions to form a semiconductor fin. The method further includes forming a gate stack, which includes forming a gate dielectric on sidewalls and a top surface of the semiconductor fin, and depositing a titanium nitride layer over the gate dielectric as a work-function layer. The titanium nitride layer is deposited at a temperature in a range between about 300° C. and about 400° C. A source region and a drain region are formed on opposing sides of the gate stack.

## Claims

### Claim 1

A device, comprising:
a first semiconductor region;
a first gate stack on the first semiconductor region, the first gate stack comprising:
a first gate dielectric; and
a first titanium nitride layer over and contacting the first gate dielectric, wherein the first titanium nitride layer has a first (200)/(111) signal intensity ratio greater than 1.4; and
a first p-type source region and a first p-type drain region on opposing sides of the first gate stack.

### Claim 2 (depends on 1)

The device of claim 1, further comprising a second titanium nitride layer over the first titanium nitride layer, wherein the second titanium nitride layer has a second (200)/(111) signal intensity ratio different from the first (200)/(111) signal intensity ratio.

### Claim 3 (depends on 2)

The device of claim 2, wherein the second (200)/(111) signal intensity ratio is smaller than the first (200)/(111) signal intensity ratio.

### Claim 4 (depends on 2)

The device of claim 2, further comprising an n-type work function layer between the first titanium nitride layer and the second titanium nitride layer.

### Claim 5 (depends on 2)

The device of claim 2, wherein the first titanium nitride layer is in physical contact with the second titanium nitride layer.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a second semiconductor region; and
a second gate stack on the second semiconductor region, the second gate stack comprising:
a second gate dielectric; and
a second titanium nitride layer over and contacting the second gate dielectric, wherein the second titanium nitride layer has a second (200)/(111) signal intensity ratio smaller than the first (200)/(111) signal intensity ratio; and
a second p-type source region and a second p-type drain region on opposing sides of the second gate stack.

### Claim 7

A device, comprising:
a first transistor, comprising:
a first semiconductor region;
a first high-k dielectric over the first semiconductor region; and
a first work-function layer over and contacting the first high-k dielectric, wherein the first work-function layer has a first work function, and wherein the first work-function layer has a first (200)/(111) signal intensity ratio; and
a second transistor, comprising:
a second semiconductor region;
a second high-k dielectric over and contacting the second semiconductor region; and
a second work-function layer over and contacting the second high-k dielectric, wherein the first work-function layer and the second work-function layer comprise a same material, wherein the second work-function layer has a second work function higher than the first work function, and wherein the second work-function layer has a second (200)/(111) signal intensity ratio smaller than the first (200)/(111) signal intensity ratio.

### Claim 8 (depends on 7)

The device of claim 7, wherein the first transistor and the second transistor are p-type transistors, and the second work function is greater than the first work function by more than 20 mV.

### Claim 9 (depends on 7)

The device of claim 7, wherein the first transistor and the second transistor are p-type transistors, and the first work-function layer and the second work-function layer comprise titanium nitride.

### Claim 10 (depends on 7)

The device of claim 7, further comprising:
a third work-function layer over and contacting the first work-function layer, wherein the third work-function layer and the second work-function layer comprise a same material, and wherein the third work-function layer has the second work function.

### Claim 11 (depends on 7)

The device of claim 7, wherein the first (200)/(111) signal intensity ratio greater than 1.4.

### Claim 12 (depends on 7)

The device of claim 7, further comprising a glue layer over the second work-function layer of the second transistor, wherein the glue layer and the second work-function layer comprise a same material, and wherein the glue layer has a third (200)/(111) signal intensity ratio equal to the second (200)/(111) signal intensity ratio.

### Claim 13 (depends on 7)

The device of claim 7, wherein the first work-function layer is a composite layer comprising a titanium silicon nitride layer and a titanium nitride layer over the titanium silicon nitride layer.

### Claim 14 (depends on 7)

The device of claim 7, wherein the first (200)/(100) signal intensity ratio is greater than the second (200)/(100) signal intensity ratio by a difference greater than 0.35.

### Claim 15

A device, comprising:
a first transistor, comprising:
a first semiconductor region; and
a first gate electrode over the first semiconductor region, the first gate electrode comprising a first portion of a first p-type work-function layer having a first (200)/(100) signal intensity ratio, wherein the first gate electrode has a first work function;
a second transistor, comprising:
a second semiconductor region; and
a second gate electrode over the second semiconductor region, the second gate electrode comprising a first portion of a second p-type work-function layer having a second (200)/(100) signal intensity ratio, wherein the second (200)/(100) signal intensity ratio is greater than the first (200)/(100) signal intensity ratio by a difference greater than 0.35, wherein the second gate electrode has a second work function higher than the first work function; and
a third transistor, comprising:
a third semiconductor region; and
a third gate electrode over the third semiconductor region, wherein the third gate electrode has a third work function, and wherein the third work function is smaller than the first work function and the second work function.

### Claim 16 (depends on 15)

The device of claim 15, wherein the first gate electrode further comprises a second portion of the second p-type work-function layer on the first portion of the first p-type work-function layer and a first portion of an n-type work-function layer on the first portion of the second p-type work-function layer, and wherein the first work function is a p-type work function.

### Claim 17 (depends on 16)

The device of claim 16, wherein the first p-type work-function layer and the second p-type work-function layer are a same material.

### Claim 18 (depends on 16)

The device of claim 16, wherein the second gate electrode further comprises a second portion of the n-type work-function layer on the first portion of the second p-type work-function layer, and wherein the second work function is a p-type work function.

### Claim 19 (depends on 18)

The device of claim 18, wherein the third gate electrode comprises a third portion of the n-type work-function layer, and wherein the third work function is an n-type work function.

### Claim 20 (depends on 18)

The device of claim 18, wherein a chlorine atomic percentage of the second portion of the second p-type work-function layer is in a range of 1 percent and 4.5 percent.