# US 12,009,263 B2 · Methods of reducing parasitic capacitance in semiconductor devices

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- Number: US 12,009,263 B2
- Document ID: US12009263B2
- Status: Granted
- Kind: B2
- Application number: 17/350,177
- Filed: 2021-06-17
- Published: 2021-10-07
- Granted: 2024-06-11
- Earliest claimed: 2018-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kai-Hsuan Lee; Feng-Cheng Yang; Yen-Ming Chen; Sai-Hooi Yeong
- Web page: https://patentgrep.com/patent/US12009263B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/679: {comprising air gaps}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/834: {comprising FinFETs}
- H10P 95/064: {the removal being chemical etching}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/46: comprising air gaps
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10W 20/076: {in via holes or trenches}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.

## Claims

### Claim 1

A semiconductor structure, comprising:
a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), wherein the S/D feature is separated from the MG by a first air gap;
an S/D contact disposed over the S/D feature, wherein the S/D contact is separated from the MG by the first air gap, and wherein a bottom surface of the S/D contact is separated from a top surface of the S/D feature by a second air gap that is connected to the first air gap and laterally extends under the bottom surface of the S/D contact; and
a dielectric layer disposed over the first air gap.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer is a first dielectric layer, the semiconductor structure further comprising:
a gate spacer disposed between the first air gap and the MG, the gate spacer including a first dielectric material having a first dielectric constant; and
a second dielectric layer disposed between a sidewall of the S/D contact and the first air gap, the second dielectric layer including a second dielectric material having a second dielectric constant, wherein the first dielectric constant is different from the second dielectric constant.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the second dielectric constant is less than the first dielectric constant.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein the second dielectric material is air.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the S/D contact includes a metal silicide layer and a metal conductive layer, wherein the metal silicide layer is disposed between the metal conductive layer and the S/D feature.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein a width of the metal silicide layer is less than a width of the S/D feature.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the dielectric layer partially fills the first air gap.

### Claim 8

A semiconductor structure, comprising:
a semiconductor fin disposed over a substrate;
a metal gate stack (MG) disposed over the semiconductor fin;
a source/drain (S/D) feature disposed over the semiconductor fin and adjacent to the MG;
an S/D contact disposed over the S/D feature;
an air gap disposed between the S/D contact and the MG, wherein a first portion of the air gap is disposed along a sidewall of the S/D contact, wherein a second portion of the air gap is disposed along a sidewall of the S/D feature, and wherein a third portion of the air gap is disposed at an interface between the S/D contact and the S/D feature; and
a dielectric layer partially filling the first portion of the air gap.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, further comprising a silicide layer disposed between the S/D contact and the S/D feature, wherein a portion of the silicide layer is separated from a top surface of the S/D feature by the third portion of the air gap.

### Claim 10 (depends on 8)

The semiconductor structure of claim 8, wherein the dielectric layer is a first dielectric layer, the semiconductor structure further comprising a second dielectric layer disposed along the sidewall of the S/D contact, wherein the second dielectric layer is separated from the MG by the first portion of the air gap.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the first portion of the air gap has the same width as the second portion of the air gap.

### Claim 12 (depends on 8)

The semiconductor structure of claim 8, wherein the first portion of the air gap directly exposes the sidewall of the S/D contact.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the first portion of the air gap is wider than the second portion of the air gap.

### Claim 14 (depends on 8)

The semiconductor structure of claim 8, wherein the S/D contact includes cobalt.

### Claim 15

A semiconductor structure, comprising:
a source/drain (S/D) feature disposed over a semiconductor fin;
a metal gate stack disposed adjacent to the S/D feature and separated from the S/D feature by a first air gap;
an S/D contact disposed over the S/D feature and separated from the metal gate stack by the first air gap;
a silicide layer disposed between the S/D feature and the S/D contact, wherein a portion of a bottom surface of the silicide layer is separated from the S/D feature along a vertical direction by a second air gap; and
a seal layer disposed over the first air gap.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the silicide layer is configured to have a curvature such that a middle portion of the silicide layer adjacent to the second air gap directly contacts the S/D feature.

### Claim 17 (depends on 15)

The semiconductor structure of claim 15, wherein the seal layer partially penetrates the first air gap.

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, wherein the seal layer includes a first dielectric material, and wherein the semiconductor structure includes a second dielectric material disposed along a sidewall of the S/D contact.

### Claim 19 (depends on 18)

The semiconductor structure of claim 18, wherein the second dielectric material includes a low-k dielectric material.

### Claim 20 (depends on 15)

The semiconductor structure of claim 15, wherein a width of the first air gap adjacent to the S/D contact is greater than a width of the first air gap adjacent to the S/D feature.