# US 12,009,262 B2 · Semiconductor device having planar transistor and FinFET

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- Number: US 12,009,262 B2
- Document ID: US12009262B2
- Status: Granted
- Kind: B2
- Application number: 17/740,241
- Filed: 2022-05-09
- Published: 2022-08-18
- Granted: 2024-06-11
- Earliest claimed: 2017-08-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Barn Chen; Ting-Huang Kuo; Shiu-Ko Jangjian; Chi-Cherng Jeng; Kuang-Yao Lo
- Web page: https://patentgrep.com/patent/US12009262B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/834: {comprising FinFETs}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A device includes a FinFET on a first region of a substrate and a planar-FET on a second region of the substrate. The FinFET includes a FinFET source region, a FinFET drain region, and a FinFET gate between the FinFET source region and the FinFET drain region. The planar-FET includes a planar-FET source region, a planar-FET drain region, and a planar-FET gate between the planar-FET source region and the planar-FET drain region. A bottommost position of the FinFET source region is lower than a bottommost position of the planar-FET source region.

## Claims

### Claim 1

A device, comprising:
a first transistor on a first region of a substrate, the first transistor comprising a first gate structure over the first region, a first source and a first drain on opposite sides of the first gate structure;
a second transistor on a second region of the substrate, the second transistor comprising a second gate structure over a protruding structure protruding from the second region of the substrate, a second source and a second drain on opposite sides of the second gate structure;
a first gate spacer on a sidewall of the second gate structure with a bottommost surface on the second source, wherein a bottommost surface of the first source is higher than the bottommost surface of the first gate spacer;
a first dielectric region directly below the first gate structure; and
a second dielectric region directly below the second gate structure, wherein the first dielectric region is continuous with the second dielectric region, wherein the first dielectric region forms an interface with the first source, and the interface has a bottommost position higher than a bottommost position of the first dielectric region.

### Claim 2 (depends on 1)

The device of claim 1, wherein the protruding structure is a fin or a channel of a three-dimensional (3D) field effect transistor (FET) structure.

### Claim 3 (depends on 1)

The device of claim 1, wherein a bottommost position of the first source and the first drain is higher than a bottommost position of the second source and the second drain.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second source and the second drain are epitaxy structures having a different profile than the first source and the first drain.

### Claim 5 (depends on 1)

The device of claim 1, wherein the second gate structure has a taller height than the first gate structure.

### Claim 6 (depends on 1)

The device of claim 1, wherein the bottommost surface of the first gate spacer is lower than a bottommost surface of the first gate structure.

### Claim 7 (depends on 1)

The device of claim 1, further comprising:
a second gate spacer on a sidewall of the first gate structure.

### Claim 8 (depends on 7)

The device of claim 7, wherein a bottommost surface of the second gate spacer is higher than the bottommost surface of the first gate spacer.

### Claim 9 (depends on 1)

The device of claim 1, wherein the first dielectric region and the second dielectric region has a non-zero thickness difference greater than a non-zero height difference between the bottommost surface of the first source and a bottommost surface of the second source.

### Claim 10

A device, comprising:
a non-planar field effect transistor (FET) on a first region of a substrate, the non-planar FET comprising a first source region, a first drain region, and a first gate between the first source region and the first drain region;
a planar-FET on a second region of the substrate, the planar-FET comprising a second source region, a second drain region, and a second gate between the second source region and the second drain region,
wherein a bottommost position of the first source region is lower than a bottommost position of the second source region;
a first dielectric region directly below the first gate of the non-planar FET; and
a second dielectric region directly below the second gate of the planar-FET, wherein the second dielectric region is continuous with the first dielectric region, and the first source region is an epitaxial region having a width varying as a function of height, and the varying width of the epitaxial region has a maximum value at a position lower than a top surface of the second dielectric region.

### Claim 11 (depends on 10)

The device of claim 10, wherein a bottommost position of the first drain region is lower than a bottommost position of the second drain region.

### Claim 12 (depends on 10)

The device of claim 10, wherein a bottommost position of the first gate is lower than a bottommost position of the second gate.

### Claim 13 (depends on 10)

The device of claim 10, wherein the first gate has a taller height than the second gate.

### Claim 14 (depends on 10)

The device of claim 10, wherein the first gate has a bottommost position lower than the bottommost position of the second source region.

### Claim 15 (depends on 10)

The device of claim 10, wherein the first gate has a bottommost position lower than a bottommost position of the second drain region.

### Claim 16 (depends on 10)

The device of claim 10, wherein the second gate has a bottommost position higher than the bottommost position of the first source region.

### Claim 17 (depends on 10)

The device of claim 10, wherein the second gate has a bottommost position higher than a bottommost position of the first drain region.

### Claim 18

A device, comprising:
a first transistor on a substrate, and comprising first source/drain regions, a first channel region between the first source/drain regions, and a first gate on multiple sides of the first channel region;
a second transistor on the substrate, and comprising second source/drain regions, a second channel region between the second source/drain regions, and a second gate on a top side of the second channel region;
a first gate spacer spacing the first gate from one of the first source/drain regions;
a second gate spacer spacing the second gate from one of the second source/drain regions, wherein the second gate spacer has a bottom surface higher than a bottom surface of the first gate spacer; and
an isolation structure between the first transistor and the second transistor, the isolation structure having a stepped top surface having a higher region and a lower region lower than the higher region, the lower region being directly below the first gate, and the higher region being directly below the second gate, wherein a depth of the second source/drain regions of the second transistor is smaller than a height difference between the higher region and the lower region of the stepped top surface of the isolation structure.

### Claim 19 (depends on 18)

The device of claim 18, wherein the bottom surface of the second gate spacer is higher than bottom surfaces of the first source/drain regions.

### Claim 20 (depends on 18)

The device of claim 18, wherein the higher region of the stepped top surface of the isolation structure is level with top surfaces of the second source/drain regions.