# US 12,009,261 B2 · Nanosheet devices with hybrid structures and methods of fabricating the same

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- Number: US 12,009,261 B2
- Document ID: US12009261B2
- Status: Granted
- Kind: B2
- Application number: 17/520,385
- Filed: 2021-11-05
- Published: 2022-08-11
- Granted: 2024-06-11
- Earliest claimed: 2021-02-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Chiang; Shi Ning Ju; Guan-Lin Chen; Jung-Chien Cheng; Chih-Hao Wang; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US12009261B2

## CPC

- H10D 84/0128: {Manufacturing their channels}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first stack of active channel layers disposed over a semiconductor substrate;
a second stack of active channel layers disposed over the semiconductor substrate;
a dummy channel layer disposed within the second stack, wherein the first stack is free of any dummy channel layer;
a gate structure engaged with the first stack and the second stack; and
first source/drain (S/D) features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, wherein the second S/D features overlap with the dummy channel layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first stack includes a first number of active channel layers, the second stack includes a second number of active channel layers, and the second stack includes a third number of the dummy channel layers, and wherein a sum of the second number and the third number is equal to the first number.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the third number ranges from one to one less than the first number.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the dummy channel layer includes a first dopant species and the second S/D features include a second dopant species that has a conductivity type different from that of the first dopant species.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the dummy channel layer includes a semiconductor material doped with a p-type dopant or an n-type dopant, and wherein each active channel layer in the first stack and the second stack is free of any dopant.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the first S/D features and the second S/D features each include a doped semiconductor layer and have the same depth.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the doped semiconductor layer of the second S/D features overlaps with the dummy channel layer.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the first S/D features include a first doped semiconductor layer disposed over an un-doped semiconductor layer and the second S/D features include a second doped semiconductor layer disposed over the un-doped semiconductor layer, and wherein the first doped semiconductor layer extends to below the second doped semiconductor layer.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the un-doped semiconductor layer in the second S/D features overlaps with the dummy channel layer.

### Claim 10

A semiconductor structure, comprising:
a first fin structure including a first stack of active channel layers and protruding from a substrate;
a second fin structure including a second stack of active channel layers disposed over at least one dummy channel layer and protruding from the substrate;
a gate structure engaged with the first stack and the second stack;
a first source/drain (S/D) feature disposed in the first fin structure and adjacent to the first stack, wherein the first S/D feature includes a first doped epitaxial layer over an un-doped epitaxial layer; and
a second S/D feature disposed in the second fin structure and adjacent to the second stack, wherein the second S/D feature includes a second doped epitaxial layer over the un-doped epitaxial layer, and wherein the un-doped epitaxial layer overlaps with the at least one dummy channel layer.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the at least one dummy channel layer includes a first dopant and the second S/D feature includes a second dopant, and wherein the first dopant and the second dopant differ in conductivity type.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, wherein a total number of the at least one dummy channel layer and the active channel layers in the second stack is the same as a total number of the active channel layers in the first stack.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, further comprising:
a third fin structure including a third stack of active channel layers and protruding from the substrate, wherein the first stack and the third stack include the same number of the active channel layers; and
a third S/D feature disposed in the third fin structure and adjacent to the first stack, wherein the third S/D feature includes a third doped epitaxial layer over the un-doped epitaxial layer, and wherein the first S/D feature extends to below the third S/D feature.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein a first number of the active channel layers in the first stack that overlap with the first S/D feature is greater than a second number of the active channel layers in the third stack that overlap with the third S/D feature.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, wherein an offset between a bottom surface of the first S/D feature and the third S/D feature is greater than a thickness of the un-doped epitaxial layer.

### Claim 16

A method, comprising:
providing a semiconductor substrate having a first region and a second region;
forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin includes a first stack of active channel layers and the second fin includes a second stack of active channel layers disposed over at least one dummy channel layer, and wherein the active channel layers and the at least one dummy channel layer have different compositions;
forming a dummy gate stack over the first fin and the second fin;
forming first source/drain (S/D) features in the first fin and second S/D features in the second fin, wherein the second S/D features overlap with the at least one dummy channel layer; and
replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack is formed adjacent to the first S/D features and the second S/D features.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the first fin and the second fin includes:
forming a sacrificial layer over the semiconductor substrate;
forming a bottommost active channel layer over the sacrificial layer;
selectively performing an implantation process to a portion of the bottommost active channel layer disposed in the second region with respect to a portion of the bottommost active channel layer disposed in the first region;
thereafter, alternatingly forming the sacrificial layers and the active channel layers over the bottommost active channel layer to form a stack; and
patterning the stack to form the first fin and the second fin.

### Claim 18 (depends on 16)

The method of claim 16, wherein a total number of the active channel layers and the at least one dummy channel layer in the second stack is the same as a total number of the active channel layers in the first stack.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the first S/D features and the second S/D features include:
forming a first S/D recess in the first fin and a second S/D recess in the second fin;
epitaxially growing a first semiconductor layer in the first S/D recess and the second S/D recess, wherein the first semiconductor layer is free of any dopant species, and wherein the first semiconductor layer overlaps with the at least one dummy channel layer; and
epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer includes a dopant species.

### Claim 20 (depends on 16)

The method of claim 16, wherein the active channel layers are free of any dopant species, the at least one dummy channel layer includes a first dopant species, and the second S/D features includes a second dopant species, and wherein the first dopant species and the second dopant species have different conductivity types.