# US 12,009,259 B2 · Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof

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- Number: US 12,009,259 B2
- Document ID: US12009259B2
- Status: Granted
- Kind: B2
- Application number: 17/460,405
- Filed: 2021-08-30
- Published: 2023-03-02
- Granted: 2024-06-11
- Earliest claimed: 2021-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Sheng-Tsung Wang; Chia-Hao Chang; Lin-Yu Huang; Cheng-Chi Chuang; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US12009259B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/514: {characterised by the insulating layers}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/42: Vias, e.g. via plugs
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
depositing a sacrificial metal contact etch stop layer (M-CESL) over a first interlayer dielectric layer (ILD) having a source/drain metal contact formed therein, wherein an isolation feature is formed above the source/drain metal contact;
depositing a second ILD layer over the sacrificial M-CESL layer;
forming a contact opening by patterning the second ILD layer and the sacrificial M-CESL layer;
filling the contact opening with a conductive material;
performing a planarization process to remove the second ILD layer and the conductive material in the second ILD layer to expose the sacrificial M-CESL layer;
removing the sacrificial M-CESL layer; and
depositing a low-k dielectric layer to cover the conductive material.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a sacrificial self-aligned contact (SAC) layer over a gate electrode layer in the first ILD layer,
wherein forming the contact opening comprises etching the isolation feature over the source/drain metal contact using the sacrificial SAC layer as an etch stop layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
removing the sacrificial SAC layer to form a cavity over the gate electrode layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein removing the sacrificial M-CESL layer and the sacrificial SAC layer are performed during the same etching process.

### Claim 5 (depends on 3)

The method of claim 3, wherein depositing the low-k dielectric layer comprises filling the cavity over the gate electrode layer.

### Claim 6 (depends on 2)

The method of claim 2, further comprising:
depositing a metal gate liner over the gate electrode layer prior to forming the sacrificial SAC layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
etching sidewall spacers on both sides of the gate electrode layer prior to depositing the metal gate liner.

### Claim 8

A method for forming a semiconductor device, comprising:
depositing an interlayer dielectric (ILD) layer over first and second source/drain features;
forming a first source/drain metal contact in the ILD layer and in contact with the first source/drain feature;
etching back the first source/drain metal contact;
depositing a first isolation feature over the first source/drain metal contact;
depositing a sacrificial metal contact etch stop layer (M-CESL) over the first solation feature and ILD layer;
patterning the sacrificial M-CESL and removing the first isolation feature;
forming a conductive feature on the first source/drain metal contact, wherein a first portion of the conductive feature is embedded in the sacrificial M-CESL, a second portion of the conductive feature is embedded in the ILD layer, and the first portion is wider than the second portion; and
replacing the sacrificial M-CESL with a low-k dielectric layer, wherein the low-k dielectric layer has having a top surface and a lower surface, the lower surface is in contact with the ILD layer, and a first portion of the low-k dielectric layer extends upward from the lower surface.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a gate electrode layer between the first and second source/drain features, wherein a second portion of the low-k dielectric layer is disposed over the gate electrode layer, and the second portion of the low-k dielectric layer extends downward from the lower surface.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a sacrificial self-aligned contact (SAC) layer over the gate electrode layer and replacing the sacrificial SAC layer with the low-k dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a metal gate liner over the gate electrode layer prior to forming the sacrificial SAC layer, wherein the metal gate liner is disposed over the second portion of the low-k dielectric layer and the gate electrode layer.

### Claim 12 (depends on 9)

The method of claim 9, wherein the gate electrode layer is formed between two sidewall spacers, wherein the second portion of the low-k dielectric layer is disposed between the two sidewall spacers.

### Claim 13 (depends on 12)

The method of claim 12, wherein the sidewall spacers are in contact with the low-k dielectric layer at the lower surface.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
forming a second source/drain metal contact in the ILD layer and in contact with the second source/drain feature; and
forming a second isolation feature in contact with the second source/drain metal contact, wherein the lower surface of the low-k dielectric layer is in contact with the second isolation feature.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second isolation feature comprises a low-k dielectric material.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second isolation feature and the low-k dielectric layer are formed from the same low-k dielectric material.

### Claim 17

A method for forming a semiconductor device, comprising:
forming first and second source/drain features;
depositing a first interlayer dielectric layer (ILD) over the first and second source/drain features;
forming a gate electrode layer between the first and second source/drain features;
forming a sacrificial self-aligned contact (SAC) layer above the gate electrode layer;
forming first and second source/drain metal contacts above the first and second source/drain features and through the first ILD layer, wherein first and second sidewall spacers are disposed between the gate electrode layer and the first and second source/drain metal contacts;
depositing a sacrificial metal contact etch stop layer (M-CESL) above the SAC layer;
depositing a sacrificial ILD layer over the sacrificial M-CESL; and
forming a conductive feature, wherein the conductive feature has a first portion embedded in the sacrificial M-CESL and a second portion in contact with the first source/drain metal contact, and the first portion of the conductive feature is in contact with the SAC layer;
removing the sacrificial ILD layer;
replacing the sacrificial M-CESL with a low-k dielectric material; and
replacing the sacrificial SAC layer with the low-k dielectric material.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming an isolation feature in contact with the second source/drain metal contact and the sacrificial M-CESL.

### Claim 19 (depends on 18)

The method of claim 18, wherein the isolation feature comprises a low-k dielectric material.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
removing the sacrificial M-CESL layer and the sacrificial SAC layer during the same etching process.