# US 12,009,258 B2 · Self-aligned interconnect with protection layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,009,258 B2
- Document ID: US12009258B2
- Status: Granted
- Kind: B2
- Application number: 17/227,056
- Filed: 2021-04-09
- Published: 2021-07-22
- Granted: 2024-06-11
- Earliest claimed: 2014-06-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Chan Yen; Ching-Feng Fu; Chia-Ying Lee
- Web page: https://patentgrep.com/patent/US12009258B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

## Claims

### Claim 1

A method comprising:
forming a first inter-layer dielectric (ILD) over a substrate and adjacent a gate stack, gate spacers being on sidewalls of the gate stack, the gate spacers being between the gate stack and the first ILD;
forming a second ILD over the first ILD;
etching the second ILD to form a first contact opening, the first contact opening exposing the first ILD and at least one of the gate spacers;
forming a dielectric protection layer on opposite sidewalls of the first contact opening;
forming a first contact plug in the first contact opening, with the first contact plug being between opposite portions of the dielectric protection layer;
etching the first contact plug to form a first recess between the opposite portions of the dielectric protection layer;
forming a dielectric capping layer in the first recess over and contacting the first contact plug, the dielectric capping layer further contacting the opposite portions of the dielectric protection layer;
forming a third ILD over the second ILD;
forming a second contact opening in the second ILD and the third ILD; and
filling the second contact opening to form a second contact plug.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the dielectric capping layer comprises:
filling the dielectric capping layer in the first recess; and
planarizing the dielectric capping layer, wherein a top surface of the dielectric capping layer is level with a top surface of the second ILD.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the second contact opening exposes the dielectric protection layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein an etchant selected for forming the second contact opening has an etching selectivity greater than 10 for materials of the third ILD and the second ILD relative to materials of the dielectric protection layer.

### Claim 5 (depends on 1)

The method of claim 1 further comprising forming an etch stop layer over the first ILD before the forming the second ILD, wherein the first contact opening penetrates through the etch stop layer.

### Claim 6 (depends on 1)

The method of claim 1 further comprising forming a source/drain contact plug in the second ILD and the third ILD simultaneously when the second contact plug is formed.

### Claim 7

A method comprising:
forming a gate stack with gate spacers over a semiconductor substrate;
forming a first inter-layer dielectric (ILD) over the semiconductor substrate and adjacent the gate stack and the gate spacers;
forming a second ILD over the first ILD, the gate stack, and the gate spacers;
forming a first opening in the second ILD;
forming a dielectric protection layer in the first opening, the dielectric protection layer physically contacting the first ILD and at least one of the gate spacers;
anisotropically etching the dielectric protection layer;
forming a contact plug filling the first opening;
etching back the contact plug to form a first recess;
depositing a dielectric capping layer filling the first recess; and
planarizing the dielectric capping layer, wherein a top surface of the dielectric capping layer is coplanar with a top surface of the dielectric protection layer and a top surface of the second ILD after planarizing the dielectric capping layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
depositing a third ILD over the second ILD, the dielectric protection layer, and the dielectric capping layer; and
etching the third ILD, the dielectric protection layer, and the dielectric capping layer to form a second opening exposing a surface of the contact plug.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a second contact plug in the second opening, wherein a first width of the contact plug measured from a first sidewall of the dielectric protection layer to a second sidewall of the dielectric protection layer is greater than a second width of the second contact plug measured from a third sidewall of the dielectric protection layer to a fourth sidewall of the dielectric protection layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein etching the third ILD, the dielectric protection layer, and the dielectric capping layer to form the second opening removes the dielectric capping layer from a first portion of the surface of the contact plug, wherein the dielectric capping layer remains over a second portion of the surface of the contact plug.

### Claim 11 (depends on 7)

The method of claim 7, wherein the dielectric protection layer and the dielectric capping layer are formed of a same material.

### Claim 12 (depends on 7)

The method of claim 7, further comprising forming an etch stop layer over the semiconductor substrate before forming the second ILD, wherein the first opening is formed through the etch stop layer.

### Claim 13

A method comprising:
forming a gate stack with gate spacers over a semiconductor substrate;
forming a first inter-layer dielectric (ILD) over the semiconductor substrate and surrounding the gate stack;
depositing a second ILD over the first ILD;
etching through the second ILD to form a first opening;
forming a dielectric protection layer on opposite sidewalls of the first opening, the dielectric protection layer physically contacting the first ILD and at least one of the gate spacers;
forming a first contact plug filling the first opening, the first contact plug extending between opposite inner sidewalls of the dielectric protection layer;
etching back the first contact plug to form a first recess;
forming a dielectric capping layer in the first recess, wherein the dielectric capping layer is in contact with the first contact plug, and wherein the dielectric capping layer is in contact with the opposite inner sidewalls of the dielectric protection layer;
etching through the dielectric capping layer to form a second opening exposing a top surface of the first contact plug; and
forming a second contact plug in the second opening.

### Claim 14 (depends on 13)

The method of claim 13, further comprising planarizing the first contact plug, the second ILD, and the dielectric protection layer before etching back the first contact plug.

### Claim 15 (depends on 14)

The method of claim 14, further comprising planarizing the dielectric capping layer, the second ILD, and the dielectric protection layer before etching through the dielectric capping layer.

### Claim 16 (depends on 13)

The method of claim 13, wherein the first opening is formed with a first width, wherein the second opening is formed with a second width, and wherein the first width is greater than the second width.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first contact plug is formed with a third width, wherein the second contact plug is formed with the second width, and wherein the second width is greater than the third width.

### Claim 18 (depends on 13)

The method of claim 13, further comprising depositing a third ILD over the second ILD, wherein the second opening is formed after depositing the third ILD over the second ILD, and wherein the second opening is formed extending through the third ILD.

### Claim 19 (depends on 15)

The method of claim 15, wherein a top surface of the dielectric capping layer is coplanar with a top surface of the dielectric protection layer and a top surface of the second ILD after planarizing the dielectric capping layer, the second ILD, and the dielectric protection layer.

### Claim 20 (depends on 1)

The method of claim 1, wherein the dielectric protection layer physically contacts the first ILD and at least one of the gate spacers.