# US 12,009,257 B2 · Semiconductor device

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- Number: US 12,009,257 B2
- Document ID: US12009257B2
- Status: Granted
- Kind: B2
- Application number: 17/874,170
- Filed: 2022-07-26
- Published: 2022-11-17
- Granted: 2024-06-11
- Earliest claimed: 2017-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chia-Hao Chang; Jia-Chuan You; Yu-Ming Lin; Chih-Hao Wang; Wai-Yi Lien
- Web page: https://patentgrep.com/patent/US12009257B2

## CPC

- H10W 20/0698: {Local interconnections}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, an interlayer dielectric (ILD) layer, an etch stop layer, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The ILD layer surrounds the conductive structure and over the gate electrode. The etch stop layer is over the conductive structure and the ILD layer. The etch stop layer comprises a material different from that of the ILD layer. A dielectric liner at a sidewall the conductive structure. The dielectric liner extends from the top surface of the source/drain contact to a bottom surface of the etch stop layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having a channel region and a source/drain region;
a gate electrode over the channel region;
a source/drain contact over the source/drain region;
a conductive structure over a top surface of the source/drain contact;
an interlayer dielectric (ILD) layer surrounding the conductive structure and over the gate electrode;
an etch stop layer over the conductive structure and the ILD layer, wherein the etch stop layer comprises a material different from that of the ILD layer, and a top surface of the conductive structure is in contact with a bottom surface of the etch stop layer;
a dielectric liner at a sidewall of the conductive structure, wherein the dielectric liner extends from the top surface of the source/drain contact to the bottom surface of the etch stop layer; and
a gate contact over the gate electrode, wherein a top surface of the gate contact is higher than a top surface of the etch stop layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1,
wherein the gate contact is electrically isolated from the conductive structure at least by the dielectric liner.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a width of the conductive structure is less than a width of the source/drain contact.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate spacer at a sidewall of the gate electrode, wherein the dielectric liner is in contact with the gate spacer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the gate contact has a sidewall having a first portion in contact with the ILD layer and a second portion in contact with the etch stop layer, and the second portion of the sidewall of the gate contact is higher than the first portion of the sidewall of the gate contact.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
a dielectric layer over the etch stop layer, wherein the sidewall of the gate contact has a third portion higher than the second portion of the sidewall of the gate contact and in contact with the dielectric layer.

### Claim 7

A semiconductor device, comprising:
a semiconductor substrate having a channel region and a source/drain region;
a gate electrode over the channel region;
a gate dielectric layer between the gate electrode and the channel region;
a gate spacer alongside the gate electrode;
a source/drain contact over the source/drain region, wherein the source/drain contact has a sidewall in contact with the gate spacer and a top surface, and an entirety of the top surface of the source/drain contact is lower than a top surface of the gate electrode and higher than a bottom surface of the gate electrode;
a conductive structure over the top surface of the source/drain contact, wherein the conductive structure has a top surface higher than the top surface of the gate electrode; and
a dielectric liner surrounding the conductive structure.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the gate electrode is free of overlapping the conductive structure when viewed from top.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the dielectric liner comprises a metal-containing compound material.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the conductive structure extends through the dielectric liner to the top surface of the source/drain contact.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, further comprising:
a gate dielectric layer between the gate electrode and the channel region, wherein the entirety of the top surface of the source/drain contact is higher than a bottommost portion of a top surface of the gate dielectric layer.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein a height of the source/drain contact is greater than a height of the source/drain region.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, wherein a height of the source/drain contact is greater than half a height of the gate electrode.

### Claim 14

A semiconductor device, comprising:
a semiconductor substrate;
a first gate electrode and a second gate electrode over the semiconductor substrate;
a source/drain contact over the semiconductor substrate and between the first and second gate electrodes, wherein the source/drain contact is made of a metal;
a first gate spacer between the source/drain contact and the first gate electrode;
a second gate spacer between the source/drain contact and the second gate electrode;
a conductive structure over the source/drain contact;
a gate contact over the first gate electrode, wherein a top surface of the gate contact is higher than a top surface of the conductive structure;
an ILD layer surrounding the conductive structure and the gate contact, wherein the ILD layer is spaced apart from the source/drain contact; and
a dielectric liner spacing the conductive structure from the ILD layer, wherein a bottom end of the dielectric liner and a bottom surface of the conductive structure are in contact with the source/drain contact.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the dielectric liner has a sidewall, an upper portion of the sidewall of the dielectric liner is in contact with the ILD layer, and a lower portion of the sidewall of the dielectric liner is in contact with the first gate spacer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the lower portion of the sidewall of the dielectric liner in contact with the first gate spacer extends upward from a top surface of the source/drain contact.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the upper portion of the sidewall of the dielectric liner in contact with the ILD layer extends downward from a top surface of the ILD layer.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein a top surface of the source/drain contact is lower than a top surface of the first gate electrode.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein a thickness of the first gate spacer is greater than a thickness of the dielectric liner.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein a height of the conductive structure is greater than a height of the source/drain contact.