# US 12,009,253 B2 · Semiconductor structure with staggered selective growth

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- Number: US 12,009,253 B2
- Document ID: US12009253B2
- Status: Granted
- Kind: B2
- Application number: 17/099,564
- Filed: 2020-11-16
- Published: 2021-03-25
- Granted: 2024-06-11
- Earliest claimed: 2018-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Zhi-Chang Lin; Teng-Chun Tsai; Wei-Hao Wu
- Web page: https://patentgrep.com/patent/US12009253B2

## CPC

- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10W 20/071: {of dielectric parts thereof}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/511: {for IGFETs}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor substrate;
a first via feature and a second via feature disposed on the semiconductor substrate; and
a staggered dielectric feature interposed between the first and second via features, wherein
the staggered dielectric feature includes a plurality of first dielectric layers and a plurality of second dielectric layers being interdigitated,
the first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material, and
each of the first dielectric layers and each of the second dielectric layers continuously extends from the first via feature to the second via feature, and contacts both the first and second via features.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising a first conductive feature and a second conductive feature disposed on the semiconductor substrate, wherein the first via feature and the second via feature are directly landing on the first and second conductive features, respectively.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, further comprising a dielectric spacer underlying and contacting the staggered dielectric feature, wherein the dielectric spacer laterally contacts both the first and second conductive features.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the staggered dielectric feature is aligned with and is completely overlapped with the dielectric spacer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein
the staggered dielectric feature spans between a first edge of the first via feature and a second edge of the second via feature,
each of the first dielectric layers has a first varying thickness decreased from the first edge to the second edge, and
each of the second dielectric layers has a second varying thickness increased from the first edge to the second edge.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein
one of the first dielectric layers has a first thickness T1 at the first edge and a second thickness T2 at the second edge;
one of the second dielectric layers has a third thickness T3 at the first edge and a fourth thickness T4 at the second edge; and
T1 is greater than T3 and T2 is less than T4.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the first dielectric material is a silicon-containing dielectric material and the second dielectric material is a metal-containing dielectric material.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the first dielectric material includes one of silicon oxide, silicon nitride and silicon oxynitride, and the second dielectric material includes one of hafnium oxide, zirconium oxide, lanthanum oxide, and aluminum oxide.

### Claim 9

A semiconductor structure, comprising:
a semiconductor substrate;
a first conductive feature and a second conductive feature disposed on the semiconductor substrate;
a first via feature and a second via feature landing on the first and second conductive features, respectively; and
a staggered dielectric feature spans between a first edge of the first via feature and a second edge of the second via feature, wherein
the staggered dielectric feature includes a plurality of first dielectric layers and a plurality of second dielectric layers being interdigitated,
the first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material,
each of the first dielectric layers continuously extends from the first edge to the second edge, and has a first varying thickness decreased from the first edge to the second edge, and
each of the second dielectric layers continuously extends from the first edge to the second edge, and has a second varying thickness increased from the first edge to the second edge.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising a dielectric spacer underlying and contacting the staggered dielectric feature, wherein the dielectric spacer laterally contacts both the first and second conductive features.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, wherein the dielectric spacer spans between the first edge and the second edge, and the dielectric spacer is completely overlapped with the staggered dielectric feature.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein
one of the first dielectric layers has a first thickness T1 at the first edge and a second thickness T2 at the second edge;
one of the second dielectric layers has a third thickness T3 at the first edge and a fourth thickness T4 at the second edge; and
T1 is greater than T3 and T2 is less than T4.

### Claim 13 (depends on 9)

The semiconductor structure of claim 9, wherein the first dielectric material is a silicon-containing dielectric material and the second dielectric material is a metal-containing dielectric material.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, wherein the first dielectric material includes one of silicon oxide, silicon nitride and silicon oxynitride, and the second dielectric material includes one of hafnium oxide, zirconium oxide, lanthanum oxide, and aluminum oxide.

### Claim 15

A method, comprising:
providing a semiconductor structure having a first conductive feature in a first region, a second conductive feature in a second region, and a dielectric spacer in a third region and interposed between the first and second conductive features;
selectively depositing a first dielectric layer of a first dielectric material in the first region, wherein the selectively depositing of the first dielectric layer includes laterally extends the first dielectric layer to the third region;
selectively depositing a second dielectric layer of a second dielectric material in the second region, wherein the selectively depositing of the second dielectric layer includes laterally extends the second dielectric layer to the third region, wherein the second dielectric material is different from the first dielectric material in composition; and
performing a first etching process to selectively etch the first dielectric material, thereby forming a first trench in the first region and leaving a staggered dielectric feature of the first and second dielectric materials in the third region.

### Claim 16 (depends on 15)

The method of claim 15, wherein
the dielectric spacer includes a first edge laterally contacting the first conductive feature and a second edge laterally contacting the second conductive feature;
the selectively depositing of the first dielectric layer includes laterally extends the first dielectric layer to the second edge; and
the selectively depositing of the second dielectric layer includes laterally extends the second dielectric layer over the first dielectric layer to the first edge.

### Claim 17 (depends on 16)

The method of claim 16, further comprising repeatedly depositing the first dielectric material and the second dielectric material to form a collective dielectric layer of the first and second dielectric materials until a thickness of the collective dielectric layer reaches a desired thickness, prior to the performing of the first etching process.

### Claim 18 (depends on 15)

The method of claim 15, wherein
the selectively depositing of the first dielectric layer includes performing a first atomic layer deposition (ALD) process using a first precursor; and
the selectively depositing of the second dielectric layer includes performing a second ALD process using a second precursor different from the first precursor.

### Claim 19 (depends on 15)

The method of claim 15, further comprising
forming a first via feature in the first trench, wherein the first via feature electrically connects to the first conductive feature;
performing a second etching process to selectively etch the second dielectric material, thereby forming a second trench in the second region; and
forming a second via in the second trench, wherein the second via feature electrically connects to the second conductive feature, wherein the first and the second via features are isolated from each other by the staggered dielectric feature.

### Claim 20 (depends on 15)

The method of claim 15, further comprising forming an inhibitor on the second conductive feature in the second region before the selectively depositing of the first dielectric layer of the first dielectric material on the first conductive feature.