# US 12,009,252 B2 · Method of making a silicon on insulator wafer

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- Number: US 12,009,252 B2
- Document ID: US12009252B2
- Status: Granted
- Kind: B2
- Application number: 17/222,554
- Filed: 2021-04-05
- Published: 2022-10-06
- Granted: 2024-06-11
- Earliest claimed: 2021-04-05
- Applicants: Alexander Yuri Usenko
- Inventors: Alexander Yuri Usenko
- Web page: https://patentgrep.com/patent/US12009252B2

## CPC

- H10P 90/1922: {using silicon etch back techniques, e.g. BESOI or ELTRAN}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.

## Claims

### Claim 1

A method for making silicon on insulator wafers comprising; preparation of device and handle wafers where said device wafer comprises a heavily doped sacrificial starting wafer covered with a stack of layers, said stack comprises etch stop layers, future cap silicon layer, and future BOX layer, said etch stop layers comprises 1st and 2nd etch stop layers where said 1st etch stop layer comprises low doped silicon epi layer over said heavily doped sacrificial starting wafer, said 2nd etch stop layer comprises heavily boron doped layer, bonding of said device wafer stack to said handle wafer, preparing bonded wafer assembly for thinning by anneal step, thinning of said device wafer stack by complete removal of said starting wafer by sequence of grinding and HNA etching, and removal of etch stop layers until said cap silicon layer is exposed characterized in that to obtain OISF free final SOI wafers, said 2nd etch stop layer is formed by a sequence of ion implantation and solid phase epitaxy, and said ion implantation uses Boron and Fluorine containing species, and said Boron concentration in said 2nd etch stop layer is equal or exceeds 1 E20 cm−3, and said concentration of Boron is achieved by solid phase epitaxy of layer amorphized by said ion implantation said cap silicon layer is grown over said 2nd etch stop layer by epitaxy after surface preparation at low temperature.

### Claim 2 (depends on 1)

The method of claim 1, where
said ion implantation comprises implanting FB2+ ion species.

### Claim 3 (depends on 2)

The method of claim 2, where
said implantation dose is chosen to cause amorphization of silicon from surface to a depth defined by implant energy.

### Claim 4 (depends on 3)

The method of claim 3, where
energy of said ions is in a range from 20 to 100 keV.

### Claim 5 (depends on 3)

The method of claim 3, where
dose of said ions is in a range from 5E14 to 5E15 cm−2.

### Claim 6 (depends on 2)

The method of claim 2, where
said boron etch stop layer is formed by electrical activation of implanted boron with solid phase epitaxy.

### Claim 7 (depends on 6)

The method of claim 6, where
said solid phase epitaxy is performed by <1 degree C./minute ramp up anneal starting from 450° C. till 600° C.

### Claim 8 (depends on 1)

The method of claim 1, where
said cap silicon layer is grown over said 2nd etch stop layer by epitaxy after surface preparation for epi at temperature below 600 C.

### Claim 9 (depends on 8)

The method of claim 8, where
said epitaxy of the cap silicon layer is performed at temperature equal or below 800 C.

### Claim 10 (depends on 9)

The method of claim 9, where
said buried oxide layer is grown from portion of said cap silicon by thermal oxidation at temperature equal or below 800° C.

### Claim 11 (depends on 1)

The method of claim 1, where
gettering anneal at 350-750° C. is performed after grinding and HNA etching steps of bonded device stack and handle wafers.